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Lauterbach M32R Manual

Debugger and trace
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M32R Debugger and Trace

Release 02.2023
MANUAL

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Summary of Contents for Lauterbach M32R

  • Page 1: M32R Debugger And Trace

    M32R Debugger and Trace Release 02.2023 MANUAL...

  • Page 2: Table Of Contents

    TRACE32 Documents ........................ ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... M32R ............................M32R Debugger and Trace ....................Introduction ........................Brief Overview of Documents for New Users Demo and Start-up Scripts Warning ..........................Quick Start ......................... Troubleshooting ........................
  • Page 3 Trace port width TrOnchip ..........................TrOnchip.RESet Resets all TO settings TrOnchip.state Opens configuration panel Security Levels of the M32R Family ................Security Level Flash Erase if Device is secured General Restrictions and Hints Floating Point Formats Integer Access Keywords JTAG Connection ......................
  • Page 4 M32R Debugger and Trace Version 10-Feb-2023 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 5: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.
  • Page 6 File menu > Search for Script. You can now search the demo folder and its subdirectories for PRACTICE start-up scripts (*.cmm) and other demo software. You can also manually navigate in the ~~/demo/m32r/ subfolder of the system directory of TRACE32. 1989-2023 ©...

  • Page 7: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 8: Quick Start

    Bus errors can be removed by executing SYStem.Up. Make sure that there isn’t any TRACE32 window open which accesses to a inaccessible memory that is not masked out, otherwise the bus error can occur again. 1989-2023 © Lauterbach M32R Debugger and Trace...
  • Page 9 /Verify that verifies all written data. This test discovers a problem with the electrical connection, wrong chip configurations or linker command file settings. For a detailed description of the Data.LOAD command and all available options, see “Data” “General Commands Reference Guide D” (general_ref_d.pdf). 1989-2023 © Lauterbach M32R Debugger and Trace...
  • Page 10 A typical start sequence for the MSC8101 is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII format) and executed with the command <file>. Other sequences can be found in the directory ~~/demo/m32r. ; Select the ICD device prompt WinClear ;...

  • Page 11: Troubleshooting

    D:XXXXXXXX and When a unrecoverable bus error occurs the target processor has to be reset. bus error generated by CPU Please refer to https://support.lauterbach.com/kb. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 12: Cpu Specific System Settings And Restrictions

    Trace features can only be used, if a special device and /or a special adapter board (Pitch-Converter) is used. Both products are provided by Renesas. SYStem.CONFIG Configure debugger according to target topology The SYSTem.CONFIG command group is not supported for the M32R. SYStem.CPU Select target CPU Format: SYStem.CPU <cpu>...

  • Page 13: System.jtagclock

    If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give debug access to another tool. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 14: System.memaccess

    JTAG port, the number of the assigned cores, and the operations that should be performed. For more information, see below. Denied No access to memory while the core is running. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 15: System.mode

    Enables program break via debug interrupt Format: SYStem.Option.DBI [ON | OFF] Default: OFF. When DBI is ON, the chip will stop faster rather than via SW control, provided the CPU offers DBI capability. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 16: System.option.imaskasm

    If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 17: System.option.keycode Code Protection

    KEYCODE command is needed. The number and location of bytes depends on the use MCU. It is normally hard coded! ; Source code example for Renesas Compiler (CPU 32192, code location ; 0x00084) .SECTION PROTECTID, DATA, ALIGN=1 ; H'0000 0084 Protect ID .DATA.B H'FF .DATA.B H'FF,H'FF,H'FF,H'FF,H'FF,H'FF,H'FF .DATA.B H'FF,H'FF,H'FF,H'FF 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 18: System.option.tristate

    SYStem.Option.TriState [ON | OFF] Default: OFF. If this option is OFF the JTAG signals and nRST line are never driven by the debugger. SYStem.state Display SYStem.state window Format: SYStem.state Displays the SYStem.state window. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 19: Trace Specific Commands

    The option can be set when the chip has trace support and defines the behavior that becomes active when the chip intern trace message FIFO buffer gets full. Stall OFF will cause losing of messages when the buffer overruns. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 20: System.option.trclk

    SYStem.Option.TRDATA [4 | 8] Default: 8. The option can be set when the chip has trace support and defines port width of the trace data. The maximum is defined by the derivatives maximum trace pin count. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 21: Tronchip

    TrOnchip The OCE unit of the M32R allows to set on-chip breakpoints. The registers are controlled by TRACE32. TRACE32 uses the on-chip trigger registers to perform on-chip breakpoints, which can be set in the Data.List window or in the dialog Breakpoint.Set. The current user interface of TRACE32 offers many possible configurations of the OCE unit.

  • Page 22: Tronchip.state Opens Configuration Panel

    TrOnchip.state Opens configuration panel Format: TrOnchip.state Control panel to configure the on-chip breakpoint and trace registers. The details are described in section TrOnchip. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 23: Security Levels Of The M32R Family

    Security Levels of the M32R Family Security Level Depending on the verification result and the security level, the following accesses to the device is possible: • Security ID code matches: Any access is possibly, there are no limitations • Security ID code does not match: Security Level 0: There is no access at all, even flashing is not possible.

  • Page 24: Flash Erase If Device Is Secured

    The JTAG clock must be limited to 1/2 of the M32 core clock. Buffers, additional loads or high capacities on the JTAG/COP lines reduce the debug speed. Trace related options only in case the device provides Trace capabilities. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 25: General Restrictions And Hints

    DIAG 0x3000 0xEB [0 | 1] (Example DIAG: 0x3000 0xEB 1 for on) 2. For the case the WDT must be feed by anyhow: Refer to DATA.TIMER.SEQUENCE and similar instructions By default external WDT support is not enabled. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 26: Floating Point Formats

    Word Word (16 bit) TByte Triple byte (24 bit) Long Double Word (32 bit), upper and lower word swapped HByte Hexabyte (48 bit) Quad Tertiary Word (64 bit), upper and lower word swapped 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 27: Jtag Connection

    VCCTRB is an output and supplies the trace date buffer on the target. Normally 1.8 V. • N/C (= Vsupply) is not connected in the ICD. This pin is used by debuggers of other manufacturers for supply voltage input. The ICD is self-powered. 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 28: Mechanical Description Of The 20-Pin Trace Connector

    TRDATA6 TRDATA7 EVENT0 EVENT1 EVENT2 EVENT3 This connector is the standard for single M32R targets. For pure debug features, this connector is not needed. Not using this connector does not impact debug features at all. Pins Connection Description Recommendations TRCLK...
  • Page 29 Target VCC Just used for voltage reference. EVENT0 Event output EVENT1 Event output EVENT2 Event output EVENT3 Event output 1989-2023 © Lauterbach M32R Debugger and Trace...

  • Page 30: Memory Classes

    Memory Classes Memory Class Description Data memory. Memory seen from the cores point of view. Program memory. 1989-2023 © Lauterbach M32R Debugger and Trace...

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