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Lauterbach C5000 Debugger Manual

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C5000 Debugger

Release 02.2022
MANUAL

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Summary of Contents for Lauterbach C5000 Debugger

  • Page 1: C5000 Debugger

    C5000 Debugger Release 02.2022 MANUAL...

  • Page 2: Table Of Contents

    TRACE32 Documents ........................ ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... TI DSPs ............................. C5000 Debugger ........................Brief Overview of Documents for New Users ..............Converter from GEL to PRACTICE .................. Warning ..........................DSP specific Implementations ..................Trigger Breakpoints...
  • Page 3 Controlling the Trace Capture Trace Breakpoints JTAG Connection ......................Mechanical Description of the 20-pin Debug Cable Electrical Description of the 20-pin Debug Cable Mechanical Description of the 14-pin Debug Cable Electrical Description of the 14-pin Debug Cable 1989-2022 © Lauterbach C5000 Debugger...
  • Page 4 Mechanical Description of the TI Connector FAQ ............................. Operation Voltage ......................1989-2022 © Lauterbach C5000 Debugger...

  • Page 5: Brief Overview Of Documents For New Users

    C5000 Debugger Version 09-Mar-2022 Brief Overview of Documents for New Users Architecture-independent information: • “Training - Debugger Basics” (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. • “T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger.

  • Page 6: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 7: Dsp Specific Implementations

    Data Value breakpoint: Number of on-chip data breakpoints that can be used to stop the program when a specific data value is written to an address or when a specific data value is read from an address. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 8: Memory Classes

    Input/Output Area Virtual Memory (memory on the debug system) Emulation Memory, Pseudo Dualport Access to Memory (see SYStem.CpuAccess) To access a memory class, write the class in front of the address. Example: Data.dump IO:0- -3 1989-2022 © Lauterbach C5000 Debugger...

  • Page 9: Dsp Specific System Commands

    <cpu>: C55XX | C5510 | OMAP1510 | OMAP1610 | LEAD3PH2 | LEAD3PH3 | … Default selection: C55XX. Selects the processor type. If your ASIC is not listed, select the type of the integrated DSP core. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 10: System.jtagclock

    JTAG frequency for TCK, independent of the RTCK signal. This frequency must be specified by the user and has to be below 1/2 of the processor clock speed. The signal RTCK clocks TDI and TMS and controls the sampling of TDO. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 11: System.memaccess

    JTAG port, the number of the assigned cores, and the operations that should be performed. For more information, see below. Denied No memory access is possible without stopping the CPU. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 12: System.mode

    Resets the target via the reset line, initializes the debug port (JTAG, SWD, cJTAG), and starts the program execution. For a reset, the reset line has to be connected to the debug connector. Program execution can, for example, be stopped by the Break command. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 13: System.config.state

    Alternatively, you can modify the target configuration settings via the TRACE32 command line with the SYStem.CONFIG commands. Note that the command line provides additional SYStem.CONFIG commands for settings that are not included in the SYStem.CONFIG.state window. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 14 CoreSight debug and trace modules and (b) informs the debugger on which memory bus and at which base address the debugger can find the control registers of the modules. For descriptions of the commands on the COmponents tab, see COmponents. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 15: System.config

    <parameter>: DAPTAP <tap> (MultiTap) DEBUGTAP <tap> ETBTAP <tap> (C5000 only) MULTITAP [NONE | IcepickA | IcepickB | IcepickC | IcepickD | IcepickBB | IcepickBC | IcepickCC | IcepickDD | JtagSEQuence <sub_cmd>] NJCR <tap> SLAVETAP <tap> 1989-2022 © Lauterbach C5000 Debugger...
  • Page 16 MEMORYAPn.RESet MEMORYAPn.view MEMORYAPn.XtorName <name> <parameter>: ADTF.Base <address> ADTF.RESet COmponents ADTF.Type [NONE | ADTF | ADTF2 | GEM] ADTF.view AET.Base <address> (C5000, C6000, C7000 only) AET.RESet (C5000, C6000, C7000 only) AET.view (C5000, C6000, C7000 only) 1989-2022 © Lauterbach C5000 Debugger...
  • Page 17 ETB.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL- STOP | FULLCTI] ETB.view <parameter>: FUNNEL.ATBSource <sourcelist> (COmponents FUNNEL.Base <address> cont.) FUNNEL.Name <string> FUNNEL.PROGrammable [ON | OFF] FUNNEL.RESet FUNNEL.view OCP.Base <address> OCP.RESet OCP.TraceID <id> OCP.view PMI.Base <address> PMI.RESet PMI.TraceID <id> PMI.view 1989-2022 © Lauterbach C5000 Debugger...
  • Page 18 TPIU.view <parameter>: TRACEPORT.Name (Components TRACEPORT.RESet cont.) TRACEPORT.TraceSource TRACEPORT.Type TRACEPORT.view TRC.Base <address> (C7000 only) TRC.RESet (C7000 only) TRC.view (C7000 only) <parameter>: COREBASE <address> (Deprecated) CTIBASE <address> DEBUGBASE <address> ETBBASE <address> ETBFUNNELBASE <address> ETFBASE <address> ETMBASE <address> 1989-2022 © Lauterbach C5000 Debugger...
  • Page 19 SYStem.CONFIG command. The SYStem.CONFIG command information shall be provided after the SYStem.CPU command, which might be a precondition to enter certain SYStem.CONFIG commands, and before you start up the debug session e.g. by SYStem.Up. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 20: Parameters> Describing The "Debugport

    But sometimes it is a must to tell the debugger that these cores share resources on the same <chip>. Whereby the “chip” does not need to be identical with the device on your target board: debugger#1: <core>=1 <chip>=1 debugger#2: <core>=2 <chip>=1 1989-2022 © Lauterbach C5000 Debugger...
  • Page 21 JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). The other debuggers need to have the setting Slave ON. Default: OFF. Default: ON if CORE=... >1 in the configuration file (e.g. config.t32). 1989-2022 © Lauterbach C5000 Debugger...
  • Page 22 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 23: Parameters> Describing The "Jtag" Scan Chain And Signal Behavior

    TDO signal. See possible TAP types and example below. Default: 0. NOTE: If you are not sure about your settings concerning IRPRE, IRPOST, DRPRE, and DRPOST, you can try to detect the settings automatically with the SYStem.DETECT.DaisyChain command. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 24 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 25 Example: ARM11 TAP ETB TAP OfNoInterest TAP DAP TAP IR: 5bit IR: 4bit IR: 7bit IR: 4bit SYStem.CONFIG IRPRE 15. SYStem.CONFIG DRPRE SYStem.CONFIG DAPIRPOST 16. SYStem.CONFIG DAPDRPOST SYStem.CONFIG ETBIRPOST SYStem.CONFIG ETBDRPOST SYStem.CONFIG ETBIRPRE SYStem.CONFIG ETBDRPRE 1989-2022 © Lauterbach C5000 Debugger...
  • Page 26 1989-2022 © Lauterbach C5000 Debugger...

  • Page 27: Parameters> Describing A System Level Tap "Multitap

    TAP in the JTAG chain. E.g. ARM11 TAP if you intend to debug an ARM11. Used if MULTITAP=Icepickx. ETBTAP <tap> Specifies the TAP number which needs to be activated to get the ETB TAP in the JTAG chain. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 28 Number of a Non-JTAG Control Register (NJCR) which shall be used by the debugger. Used if MULTITAP=Icepickx. SLAVETAP <tap> Specifies the TAP number to get the Icepick of the sub-system in the JTAG scan chain. Used if MULTITAP=IcepickXY (two Icepicks). 1989-2022 © Lauterbach C5000 Debugger...

  • Page 29: Parameters> Configuring A Coresight Debug Access Port "Ap

    “Port” or “Base” (with “DP:” access) in case XtorName remains empty. Example 1: SoC-400 SoC-400 ROM table Memory Access Port CoreSight (MEM-AP) Component Debug ROM table Memory Port Access Port (DP) (MEM-AP) CoreSight Component JTAG Access Port (JTAG-AP) 1989-2022 © Lauterbach C5000 Debugger...
  • Page 30 MEMORYAPn.HPROT Default: 0. [<value> | <name>] This option selects the value used for the HPROT bits in the Control Status Word (CSW) of a CoreSight Memory Access Port, when using the E: memory class. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 31 =0x06: Domain=0x0, Cache=0x6 ReadAllocateInnerShareable =0x16: Domain=0x1, Cache=0x6 ReadAllocateOuterShareable =0x26: Domain=0x2, Cache=0x6 WriteAllocateNonShareable =0x0A: Domain=0x0, Cache=0xA WriteAllocateInnerShareable =0x1A: Domain=0x1, Cache=0xA WriteAllocateOuterShareable =0x2A: Domain=0x2, Cache=0xA ReadWriteAllocateNonShareable =0x0E: Domain=0x0, Cache=0xE ReadWriteAllocateInnerShareable =0x1E: Domain=0x1, Cache=0xE ReadWriteAllocateOuterShareable =0x2E: Domain=0x2, Cache=0xE 1989-2022 © Lauterbach C5000 Debugger...
  • Page 32 ..RESet Undo the configuration for this access port. This does not cause a physical reset for the access port on the chip..view Opens a window showing the current configuration of the access port. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 33 AP access port number (0-255) of a SoC-400 system where MEMORYACCESSPORT system memory can be accessed even during runtime (typically <port> (deprecated) an AHB). Used for “E:” access class while running, assuming “SYStem.MemAccess DAP”. Default: <port>=0. SoC-600 Specific Commands 1989-2022 © Lauterbach C5000 Debugger...
  • Page 34 Example: SYStem.CONFIG.JTAGAP1.Base DP:0x80005000 Meaning: The control register block of the JTAG access ports starts at address 0x80005000. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 35: Parameters> Describing Debug And Trace "Components

    If you press the button with the three dots you get the corresponding command in the command line where you can view and maybe copy it into a script file. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 36 FUNNEL TPIU SYStem.CONFIG.COREDEBUG.Base 0x80010000 0x80012000 SYStem.CONFIG.BMC.Base 0x80011000 0x80013000 SYStem.CONFIG.ETM.Base 0x8001c000 0x8001d000 SYStem.CONFIG.STM1.Base EAHB:0x20008000 SYStem.CONFIG.STM1.Type ARM SYStem.CONFIG.STM1.Mode STPv2 SYStem.CONFIG.FUNNEL1.Base 0x80004000 SYStem.CONFIG.FUNNEL2.Base 0x80005000 SYStem.CONFIG.TPIU.Base 0x80003000 SYStem.CONFIG.FUNNEL1.ATBSource ETM.0 0 ETM.1 1 SYStem.CONFIG.FUNNEL2.ATBSource FUNNEL1 0 STM1 7 SYStem.CONFIG.TPIU.ATBSource FUNNEL2 1989-2022 © Lauterbach C5000 Debugger...
  • Page 37 HTM on port 1 and from STM on port 7. In an SMP (Symmetric MultiProcessing) debug session where you used a list of base addresses to specify one component per core you need to indicate which component in the list is meant: 1989-2022 © Lauterbach C5000 Debugger...
  • Page 38 ETM, ETR a list of base addresses to specify one component per core. Example assuming four cores: SYStem.CONFIG COREDEBUG.Base 0x80001000 0x80003000 0x80005000 0x80007000 For a list of possible components including a short description Components and Available Commands. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 39 ID (ETM.TraceID <id>). The default setting is typically fine because the debugger uses different default trace IDs for different components. For a list of possible components including a short description Components and Available Commands. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 40 NOTSET: the method is derived by other GUIs or hardware. detection. FULLSTOP: on-chip trace stack mode by implementation. FULLCTI: on-chip trace provides a trigger signal that is routed back to on-chip trace over a CTI. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 41 Selects the type of the Trace Port Interface Unit (TPIU). Generic] CoreSight: Default. CoreSight TPIU. TPIU control register located at TPIU.Base <address> will be handled by the debugger. Generic: Proprietary TPIU. TPIU control register will not be handled by the debugger. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 42 This command group is used to configure ARM Coresight Replicators with programming interface. After the Replicator(s) have been defined by the base address and optional names the ATB sources REPlicatorA and REPlicatorB can be used from other ATB sinks to connect to output A or B to the Replicator. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 43 Trace source delivering system trace information e.g. sent by software in printf() style. TPIU.ATBSource <source> TPIU.Base <address> TPIU.RESet TPIU.Type [CoreSight | Generic] Trace Port Interface Unit (TPIU) - ARM CoreSight module Trace sink sending the trace off-chip on a parallel trace port (chip pins). 1989-2022 © Lauterbach C5000 Debugger...

  • Page 44: Parameters> Which Are "Deprecated

    RAM which accesses shall be traced. The trace packages include only relative addresses to PERBASE and RAMBASE. For a list of possible components including a short description Components and Available Commands. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 45 QV1: This mode is not yet used. TIOCPTYPE <type> Specifies the type of the OCP module from Texas Instruments (TI). view Opens a window showing most of the SYStem.CONFIG settings and allows to modify them. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 46 ETMFUNNELPORT <port> FUNNEL1.ATBSource ETM <port> (1) ETMTPIUFUNNELPORT <port> FUNNEL3.ATBSource ETM <port> (1) FILLDRZERO [ON | OFF] CHIPDRPRE 0 CHIPDRPOST 0 CHIPDRLENGTH <bits_of_complete_dr_path> CHIPDRPATTERN.Alternate 0 FUNNEL2BASE <address> FUNNEL2.Base <address> FUNNELBASE <address> FUNNEL1.Base <address> HSMBASE <address> HSM.Base <address> 1989-2022 © Lauterbach C5000 Debugger...
  • Page 47 OCP.Base <address> TIOCPTYPE <type> OCP.Type <type> TIPMIBASE <address> PMI.Base <address> TISCBASE <address> SC.Base <address> TISTMBASE <address> STM1.Base <address> STM1.Mode STP STM1.Type TI TPIUBASE <address> TPIU.Base <address> TPIUFUNNELBASE <address> FUNNEL3.Base <address> TRACEETBFUNNELPORT <port> FUNNEL4.ATBSource ADTF <port> (1) 1989-2022 © Lauterbach C5000 Debugger...

  • Page 48: System.option.ahbhprot

    Enables ACE transactions on the DAP AXI-AP, including barriers. This does only work if the debug logic of the target CPU implements coherent AXI accesses. Otherwise this option will be without effect. SYStem.Option.AXICACHEFLAGS Configure AXI-AP cache bits Format: SYStem.Option.AXICACHEFLAGS <value> (deprecated) SYStem.CONFIG.AXIAPn.CacheFlags instead. Default: DeviceSYStem (=0x30: Domain=0x3, Cache=0x0). 1989-2022 © Lauterbach C5000 Debugger...

  • Page 49: System.option.axihprot

    The selected byte mode depends on the CPU registers. WORD TRACE32 interprets code in word-pointer mode. BYTE TRACE32 interprets code in byte-pointer mode. SYStem.Option.DAPDBGPWRUPREQ Force debug power in DAP Format: SYStem.Option.DAPDBGPWRUPREQ [ON | AlwaysON | OFF] Default: ON. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 50: System.option.dapsyspwrupreq

    GUIs because they cannot access the debug interface anymore. To keep the debug interface active, it is recommended that SYStem.Option.DAPDBGPWRUPREQ is set to AlwaysON. SYStem.Option.DAPSYSPWRUPREQ Force system power in DAP Format: SYStem.Option.DAPSYSPWRUPREQ [AlwaysON | ON | OFF] Default: ON. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 51: System.option.dapremap

    SWITCHTOSWD.[TryAll | None | JtagToSwd | LuminaryJtagToSwd | Dor- mantToSwd | JtagToDormantToSwd] SWDTRSTKEEP.[DEFault | LOW | HIGH] Default: SWITCHTOSWD.TryAll, SWDTRSTKEEP.DEFault. See Arm CoreSight manuals to understand the used terms and abbreviations and what is going on here. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 52: System.option.dapnoircheck

    Bug fix for derivatives which do not return the correct pattern on a DAP (Arm CoreSight Debug Access Port) instruction register (IR) scan. When activated, the returned pattern will not be checked by the debugger. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 53: System.option.dualport

    They define the TAP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target, EDBGRQ must have a pull-down resistor. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 54: System.option.entrst

    TRST line, which must not be reset together with the debug TAP. SYStem.Option.INTDIS Disable all interrupts Format: SYStem.Option.INTDIS [ON | OFF] Default: OFF. If this option is ON, all interrupts on the core are disabled. SYStem.Option.MUHP High-priority memory access Format: SYStem.Option.MUHP [ON | OFF] Default: OFF. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 55: System.option.overlay

    Data.List 0x2:0x11c4 ; Data.List <overlay_id>:<address> SYStem.Option.PWRDWN Allow power-down mode Format: SYStem.Option.PWRDWN [ON | OFF] Default: OFF. If this option is OFF, the debugger forces the chip to keep clock and keep power on OMAPxxxx devices. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 56: System.option.targetserver

    Therefore we recommend to use that option for downloading data after reset at the beginning of a debug session, only. SYStem.RESetOut Reset the DSP Format: SYStem.RESetOut This command resets the DSP. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 57: System.option.ctoolsdecoder

    SYStem.Option.CToolsDecoder [ON | OFF] Default: OFF. When this option is enabled, the TI’s cTools trace decoder software is used instead of LAUTERBACH’s trace decoder software. We recommend not to activate this option since the LAUTERBACH trace decoder software is optimized for TRACE32 software architecture. However, TI’ CToolsDecoder might be helpful for error diagnostics.

  • Page 58: Cpu Specific Benchmarkcounter Commands

    ; set a marker Alpha to the entry ; of the function sieve Break.Set V.END(sieve)-1 /Beta ; set a marker Beta to the exit ; of the function sieve BMC.<counter>.ATOB ON ; advise <counter> to count only ; in AB-range 1989-2022 © Lauterbach C5000 Debugger...

  • Page 59: Bmc..Event

    CLOCKCYCLES Clock cycles TIME TIME is measured by counting CLOCK. The translation to TIME is done by using the CPU frequency. For this reason, the CPU frequency has to be entered with the command BMC.CLOCK. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 60: Tronchip Commands

    ; sets breakpoint at range Break.Set 0x1001--0x17ff /Write ; 1000--17ff sets single breakpoint … ; at address 1001 TrOnchip.CONVert OFF ; sets breakpoint at range Break.Set 0x1000--0x17ff /Write ; 1000--17ff Break.Set 0x1001--0x17ff /Write ; gives an error message 1989-2022 © Lauterbach C5000 Debugger...

  • Page 61: C55X Specific Tronchip Commands

    Benchmark Counter - short BMCTR - collect Information about the throughput of the target processor. They count for certain events, like interrupts, cache misses or cpu cycles. This information may be helpful in finding bottlenecks and tuning the application. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 62 Activate the benchmark counter to count between the program marker Alpha and Beta only. NOTE: CMISS, INST, PINS, and INT count the number of occurrences of the corresponding event. PNULL, FNULL, and DNULL add the benchmark counter by one for every NULL cycle, which was inserted. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 63 Break.Set func13 /Program /Delta ; Set the program marker Delta /Onchip ; to the entry of func13 TrOnchip.BMCTR0 Delta ; Set the first (BMCTR0) ; benchmark counter to count ; hits on the program marker ; Delta 1989-2022 © Lauterbach C5000 Debugger...
  • Page 64 ; Instruct the benchmark counter to count ; between the program marker Alpha and Beta ; only TrOnchip.BMCTR0 PINST ; Instruct the benchmark counter to count ; for parallel instruction between Alpha and ; Beta only 1989-2022 © Lauterbach C5000 Debugger...

  • Page 65: Tronchip.clock

    Supports AET trigger optimization. TrOnchip.PROfile Display the benchmark data Format TrOnchip.PROfile [<value>] Displays the collected data of the first benchmark counter BMCTR0 in a graphical representation. In order to specify a vertical scaling, use the optional <value> parameter. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 66: Tronchip.reset Set On-Chip Trigger To Default State

    TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 67: Tracing

    Break.Set <address> | <range> /ReadWrite | /Read | /Write /TraceData Broadcast only the execution of the instruction at address 0x4dd84. Break.Set 0x1234ABCD /Program /TraceEnable … Trace.List ; display the result … Break.Delete ; delete breakpoint 1989-2022 © Lauterbach C5000 Debugger...

  • Page 68: Jtag Connection

    We strongly recommend to use a connector on your target with housing and having a center polarization (e.g. AMP: 2-827745-0). A connection the other way around indeed causes damage to the output driver of the debugger. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 69: Electrical Description Of The 20-Pin Debug Cable

    JTAG connector is tristated by the debugger and it is pulled low otherwise. This signal is normally not required, but can be used to detect the tristate state if more than one debug tools are connected to the same JTAG port. 1989-2022 © Lauterbach C5000 Debugger...

  • Page 70: Mechanical Description Of The 14-Pin Debug Cable

    The debugger will only assert a pulse on nRESET when the SYStem.Up command is executed. If it is ensured that the DSP is able to enter debug mode every time (no hang-up condition), the nRESET line is optional. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 71     EMU0 EMU1 This is a standard 14 pin double row (two rows of seven pins) connector (pin-to-pin spacing: 0.100 in.). Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2022 © Lauterbach C5000 Debugger...
  • Page 72 Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for C5500 (ICD) LA-7830 1.8 .. 3.6 V 1989-2022 © Lauterbach C5000 Debugger...

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