Table of Contents
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CP381
1-1
CP381 Product Overview ......................................................................... 1 - 4
1-2
System Relevant Information ................................................................... 1 - 6
1-3
CP381 Main Specifications ...................................................................... 1 - 9
1-5
Applied Standards .................................................................................. 1 - 10
1-6
Related Publications .............................................................................. 1 - 10
1-4
CP381 Analog Input Specifications ........................................................ 1 - 10
2-1
Pinout of the Digital Input Interface Connector CON2 ............................. 2 - 7
2-2
CompactPCI Connector CON1 (J1) ......................................................... 2 - 8
2-3
JTAG Connector (CON3) Pinout .............................................................. 2 - 9
2-4
System Status Indicators ....................................................................... 2 - 10
2-5
Function Modes of the CP381 ............................................................... 2 - 10
4-1
Backend Register Address Map .............................................................. 4 - 6
4-2
Input Data Register Bit Map ..................................................................... 4 - 7
4-3
Transparent Input Data Register Bit Map ................................................ 4 - 7
4-4
Input Control Register .............................................................................. 4 - 8
4-5
Programmable Input Sample Rates ......................................................... 4 - 8
4-6
Input Event Mask Register, Bit Map ......................................................... 4 - 9
4-7
Input Event Polarity Register, Bit Map ..................................................... 4 - 9
4-8
Input Status Register, Bit Map ................................................................. 4 - 9
4-9
Input Latch-on-Event Register, Bit Map ................................................. 4 - 10
4-10
Input Pattern Mask Register, Bit Map .................................................... 4 - 10
4-11
Input Pattern Compare Register, Bit Map .............................................. 4 - 10
4-12
Hardware Debug Register Bit Map ........................................................ 4 - 11
4-13
Hardware Status Register Bit Map ......................................................... 4 - 11
4-14
General Interrupt Enable Register, Bit Map ........................................... 4 - 12
4-15
General Interrupt Pending Register, Bit Map ......................................... 4 - 12
4-16
Input IRQ Enable Register, Bit Map ....................................................... 4 - 12
4-17
ROM Command Register Bit Map ......................................................... 4 - 13
4-18
ROM Control Register Bit Map .............................................................. 4 - 13
4-19
Opcodes and Commands ...................................................................... 4 - 14
4-20
ROM Status Register Bit Map ................................................................ 4 - 14
4-21
ROM Data Register Bit Map .................................................................. 4 - 14
ID 24107, Rev. 01
List of Tables
© 2002 PEP Modular Computers GmbH
Preface
Page ix
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