Opcodes And Commands; Rom Status Register Bit Map; Rom Data Register Bit Map - PEP CP381 Manual

30 channel compactpci digital input controller
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Configuration
Table 4-19: Opcodes and Commands
Opcode
00
10
01
Note...
The EWEN (Erase and Write Enable) command must be executed once before
the first write.
Table 4-20: ROM Status Register Bit Map
Bits
Type
31
r/w
30-0
r/w
Note...
As soon as the Startbit is set the Busy/Ready bit becomes active (Busy=1). It
remains set as long as the command is executed and is reset when command
execution is complete.
Table 4-21: ROM Data Register Bit Map
Bits
Type
31-8
r/w
7-0
r/w
Page 4 - 14
A8..A0
11xxxxxxx
xxxxxxxxx
xxxxxxxxx
Default
0
Busy/Ready
00
Reserved
Default
0
Reserved
0
Data (for data read and write commands)
© 2002 PEP Modular Computers GmbH
Command
EWEN
READ
WRITE
Function
Function
ID 24107, Rev. 01
CP381

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