Programming Interface; Access Control Logic (Address Decoder); Backend Register Address Map - PEP CP381 Manual

Configuration
4.3

Programming Interface

4.3.1

Access Control Logic (Address Decoder)

All the resources of the CP381 are mapped within the 64 kB PCI memory address space which
itself is set in the PCI configuration register BAR0. The port size of all local or backend registers
is 32-bit by default. The address map of the registers is as follows.
Table 4-1: Backend Register Address Map
Base Address
bar0 + 0x0000
0x0400
0x0800
0x0804
0x0c00
bar0 + 0x1000
0x1000
0x1400
0x1800
0x1c00
bar0 + 0x2000
0x2400
0x2408
0x240c
0x2410
0x2414
0x2418
0x241c
bar0 + 0x2800
0x2800
bar0 + 0x2c00
0x2c00
0x2c04
bar0 + 0x3000 – 0xffff
Page 4 - 6
Size
4 K Common Board Registers
32 bit g_irq General Interrupt Enable Register
32 bit hsr
32 bit i_pen General Interrupt Pending Register
32 bit hdr
4 K Capability ROM, serial EEPROM
32 bit r_cmd Command Register
32 bit r_ctl
32 bit r_sta
32 bit r_dat
2 K Input Control
32 bit i_ctl
32 bit i_irqen Input Irq Enable Register
32 bit e_pol
32 bit e_msk Input Event Mask Register
32 bit e_len
32 bit c_cmp Input Pattern Compare Register
32 bit c_msk Input Pattern Mask Register
1 K Input Status
32 bit i_event, Input Status Register
1 K Input Data
32 bit d_in, Input Data Register
32 bit input, Transparent Input Data
52 K Reserved
© 2002 PEP Modular Computers GmbH
Function
Hardware Status Register
Hardware Debug Register
Control Register
Status Register
Data Register
Input Control Register
Input Event Polarity Register
Input Latch-on-Event Register
CP381
ID 24107, Rev. 01