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Configuration
4.3.3
Debouncing Inputs
By default, all inputs are filtered through a passive analog low-pass filter placed immediately
behind the input connector. Additionally, the CP381 provides a programmable digital debounc-
er which is common for all inputs. It functions as follows; the input ports are sampled at a pro-
grammable sample rate which is derived from PCI bus clock. Two consecutive samples must
be equal before being stored in the input data register. By this means, bouncing and spikes on
inputs can be filtered out. For example, with a selected input sample rate of 500 Hz, input puls-
es which are shorter than 2 ms are filtered out.
Table 4-4: Input Control Register
Bits
Type
31-8
r/w
7
r/w
6
r/w
5
r/w
4
r/w
2-0
r/w
Note...
The Inputs are sampled through the debouncer after the Input Enable bit is set.
Additional features such as event and pattern detection and latch mode are also
enabled in the input control register, after being configured within the corre-
sponding mode registers.
Table 4-5: Programmable Input Sample Rates
Clock
deb[2..0]
Divider
000
1
001
2^8
010
2^10
011
2^12
100
2^14
101
2^16
110
2^18
111
2^20
*Note...
The clock divider default value is 1. In addition to the choice of debouncing fil-
ters, there is an analog filter implemented on board with an edge frequency at
10 kHz.
Page 4 - 8
Default
0
Reserved
0
Input enable
0
Event detect enable
0
Latch mode enable
0
Pattern detect enable
000
Debounce control deb[2..0]
Input Sample clock
@ 33MHz PCI
33 MHz
128 KHz
32 KHz
8 KHz
2 KHz
0.5 KHz
125 Hz
31 Hz
© 2002 PEP Modular Computers GmbH
Function
Input Sample period @ 33MHz PCI
30 ns
8 us
32 us
128 us
0.5 ms
2 ms
8 ms
32 ms
ID 24107, Rev. 01
CP381
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