Actel Silicon Explorer II User Manual page 39

Q: How do I tie the TRST pin during the probing using Silicon
Explorer?
A: TRST is an active low input. During JTAG mode and Silicon
Explorer debugging mode, JTAG state machine's reset must not be
active, otherwise probe circuitry is disabled. Below is the
recommendation for TRST pin in JTAG and Silicon Explorer:
RTSX Rev0 - No TRST pin
RTSX Rev1 - You must tie TRST pin high when doing JTAG and
Silicon Explorer
RTSX Rev2 - You can leave the TRST pin floating (or drive it high -
it must not be driven low) when running JTAG or Silicon Explorer
if "Reserve JTAG TRST" was selected in Designer.
SXA - You can leave the TRST pin floating when running JTAG or
Silicon Explorer
Q: What are the different options that I have to connect a device to
Silicon Explorer Probe Pilot?
A: You can connect the Silicon Explorer to the device by either
implementing a probe connector on the board for use with the
ribbon connector or by connecting the device to the Probe-Pilot
using the flying lead connector. If you choose the second
alternative, you can either use posts on your board, or the clips
provided with the Si Explorer to connect directly to the probe pins
Please refer to question 16 for information about the probe
connector dimensions.
Q: Where can I get the mechanical dimensions for the Silicon
Explorer's Probe connector?
A: Please refer to the following guru document for detailed
information about the connector.
http://www.actel.com/GURU_docs/feb00/ns853.html.
Q: Where can I find the pin layout of the Silicon Explorer?
A: The pin layout for the Silicon Explorer is found on the back of the
Silicon Explorer case. There is a notch on one side of the pin
connector that determines the position of Pin 1.
Hardware Setup
33