AOpen AX5TC User Manual page 61

AWARD BIOS
Chipset Features à Auto Configuration
Auto Configuration
When Enabled , the DRAM and cache related timing
are set to pre-defined value according to CPU type
Enabled
and clock. Select Disable if you want to specify your
Disabled
own DRAM timing.
Chipset Features à DRAM Timing
DRAM Timing
There to sets of DRAM timing parameters can be
automatically set by BIOS, 60ns and 70ns.
60 ns
70 ns
Warning : The default memory timing setting
is 60ns to get the optimal performance.
Because the specification limitation of INTEL
TX chipset , 70ns SIMM can only be used
with CPU external clock 60MHz. To use 70ns
SIMM with 66MHz CPU external clock may
result in unstable system behavior.
Chipset Features à DRAM Leadoff Timing
DRAM Leadoff
The Leadoff means the timing of first memory cycle
Timing in the burst read or write. Actually, this item controls
only
11/7/3/4
clocks of RAS precharge and RAS to CAS delay. The
10/6/3/3
four digital represent Read Leadoff/ Write Leadoff/
11/7/4/4
RAS Precharge/ RAS to CAS delay. For example,
10/6/4/3
default is 10/6/3/3, which means you have 10-x-x-x
DRAM page miss read and 6-x-x-x DRAM write, with
3 clocks RAS precharge and 3 clocks RAS to CAS
delay.
3-12
page miss read/write leadoff timing and the