JVC RX-E112RSL Service Manual page 18

RX-E112RSL/RX-E111RSL
TC9446F-025 (IC631) : Audio digital processor
1. Block diagram
4k word x3
128 word
Program
Instruction
Instruction
control
IRQ
Interrupt
2
SDIn
4
Audio
SDOn
Interface
LRCK/BCK
RX DIR
LOCK
RST
MIMD
Timer
MICS
MILP
MIDIO
MCU interface
MICK
MIACK
2. Pin function
Pin No. Symbol I/O Function
1 RST I Reset signal input terminal
(L:reset H:nomal operation)
2 MIMD I Mode select input for MCU interface
(L:serial H:IC bus)
3 MICS I Chip select input for MCU interface
4 MILP I Latch pulse input for MCU interface
5 MIDIO I/O Data I/O for MCU interface
6 MICK I Clock input for MCU interface
7 MIACK O Acknowledge output for MCU interface
8~11 FI0~3 I Flag input 0~3
12 IRQ I Interrupt input
13 VSS - Digital ground
14 LRCKA I LR clock input-A for audio interface
15 BCKA I Bit clock input-A for audio interface
16~19 SDO0~3 O Data output-0~3 for audio interface
20 LRCKB I LR clock input-B for audio interface
21 BCKB I Bit clock input-B for audio interface
22, 23 SDI0, 1 I Data input-0, 1 for audio interface
24 VDD - Digital power supply
25 LRCKOA O LR clock output-A for audio interface
26 BCKOA O Bit clock output-A for audio interface
27, 28 TEST0,1 I Test input-0, 1 (L:test H:nomal operation)
29 LRCKOB O LR clock output-B for audio interface
30 BCKOB O Bit clock output-B for audio interface
31 TXO O SPDIF output
32,33 TEST2,3 I Test input-2, 3 (L:test H:nomal operation)
34 RX I SPDIF input
35 VSS - Digital ground
36 TSTSUB0 I Test sub input-0 (L:test H:nomal operation)
37 FCONT O Frequency control output for VCO circuit
38 TSTSUB1 I Test sub input-1, 2
39 TSTSUB2 (L:test H:nomal operation)
40 PDO O Phase detect signal output
1-18
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Program
ROM
XRAM
YRAM
4k word
4k word
RAM
40 bit
X bus
Detector
Y bus
Register
1 bus
X0, X1, X2
Y0, Y2, Y3
MX MY
MAC
A1
Round/Limiter
Address Operater
x2
ERAM
CROM
X pointer
4k word Y pointer
4k word
register register
MZ AX AY
ALU
A0 A2 A3
Round/Limiter
Pin No. Symbol I/O Function
41 VDDA - Analog power supply
42 PLON I Clock selection input
(L:external clock H:VCO clock)
43 AMPI I AMP.input for LPF
44 AMPO O AMP.output for LPF
45 CKI I External clock input
46 VSSA - Analog ground
47 CKO O DIR clock output
48 LOCK O VCO lock output
49 VSS - Gigtal ground
50 WR O Writing signal output for extrenal SRAM
51 OE O Enable signal output for external SRAM
52 CE O Chip enable signal output for external SRAM
53 VDD - Digital power supply
54~61 IO7~0 I/O Data I/O-7~0 for external SRAM
62 VSS - Digital ground
63~70 AD0~7 O Address output-0~7 for external SRAM
71 VDD - Digital power supply
72~80 AD8~16 O Address output-8~16 for external SRAM
81 VSS - Digital ground
82~89 PO0~7 O General output port-0~7
90 VDDDL - Power supply for DLL circuit
91 LPFO O LPF output for DLL circuit
92 DLON I *
93 DLCKS
94 SCKO O ASP clock output
95 VSSDL - Ground for DLL circuit
96 SCKI I External system clock input
97 VSSX - Ground for crysoal oscillator
98, 99 XO,XI I/O Crystal oscillator I/O
100 VDDX - Digital power supply
*
DLCKS pin
L
L
H
H
Timing
SCKO
SCKI
DLL
DLON
LPFO
C pointer
register
Bus switch
3
CE, OE, WR
17
External SRAM
ADn
interface
8
IOn
General output 8
POn
port
4
Flag FIn
DIT
TXO
DLON pin DLL clock setting
L SCKI input (DLL circuit OFF)
H Four times XI clock
L Three times XI clock
H Six times XI clock