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This document provides a reference for the LMH0318 Reclocker from a programming model perspective.
It contains detailed information relating to programming and different configuration options. The intended
audience includes software as well as hardware engineers working on the system diagnostics and control
software.
The reader should be familiar with the LMH0318 datasheet (SNLS508). In addition to the LMH0318
datasheet, all other collateral data related to the LMH0318 Reclocker (application notes, models, etc.), are
available on the TI website. Alternatively, contact your local Texas Instruments field sales representative.
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Global Registers
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Receiver Registers
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CDR Registers
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Transmitter Registers
SNLU183 - September 2015
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Copyright © 2015, Texas Instruments Incorporated
LMH0318 Programming Guide
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List of Tables
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Programmer's Guide
SNLU183 - September 2015
LMH0318 Programming Guide
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Table of Contents
Related Manuals for Texas Instruments LMH0318
Summary of Contents for Texas Instruments LMH0318
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Page 1: Table Of Contents
The reader should be familiar with the LMH0318 datasheet (SNLS508). In addition to the LMH0318 datasheet, all other collateral data related to the LMH0318 Reclocker (application notes, models, etc.), are available on the TI website. -
Page 2: Access Methods
Register Programming via SMBus and SPI Interface The LMH0318 internal registers can be accessed through standard SMBus or SPI protocol. The SMBUS Mode is enabled by setting MODE_SEL pin = LOW (1 kΩ to GND). Pins associated with SMBus interface... -
Page 3: Register Programming Via Spi
The LMH0318 register set is divided into four groups: • Global Registers- These registers are divided into share and channel registers. Share register define LMH0318 ID, revision, enabling shared registers. Channels registers are feature specific such as interrupt status or interrupt mask •... -
Page 4: Initialization Set Up
Initialization Set Up www.ti.com Initialization Set Up After power up or register reset write the initialization sequences: Table 1. LMH0318 Register Initialization DESCRIPTION ADDRESS [Hex] VALUE [Hex] Enable Channel Registers 0xFF 0x04 Enable Full Temperature Range 0x16 0x25 0x3E 0x00... -
Page 5: Register Command Syntax
● It is recommended to issue CDR Reset and Release after changing register settings that alters CDR state machine ● See Register Tables for further details on register bit definitions SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated... -
Page 6: Device Configuration
Common Device Configuration The LMH0318 supports SMPTE data rates. Once configured for SMPTE application, the LMH0318 can be optioned to lock to a selection of data rates and report lock status. The following is an example of common register settings for the LMH0318 initialization followed by possible settings to support SMPTE data rates. -
Page 7: Common Register Commands
Note: Share register 0xFF can be written/read all the time and does not require selection of share register bank. 4.2.2 LMH0318 Reset Registers The LMH0318 has two reset functions: CDR State Machine Reset and Register Reset. 4.2.2.1 LMH0318 CDR State Machine Reset This operation should be done after changing any of the channel registers. - Page 8 4.2.3 Force Power Down The ENABLE pin (#6) can be used to force the LMH0318 in power down. Additionally, the LMH0318 powers down when there is loss of signal (selected channel Signal Detect is not asserted). There could be a need to power down the device even when there is active signal. This could be achieved either by disabling ENABLE pin or forcing the signal detect de-asserted and thus powering down the selected channel.
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Page 9: Smpte Data Rate Selection
Check Status of LOS (Loss Of Signal) on Input 1 or Input 0 The LMH0318 has two inputs and each input has its own signal detector. Based on signal detect status and input channel selected, the device automatically goes into power down. For example, if IN0 is selected and there is no signal on IN0 then the device, CDR and output drivers go into power down. -
Page 10: Ctle Boost Setting Vs Media Trace Length
Device Configuration www.ti.com 4.2.6 Input/Output Selection The LMH0318 has 2:1 Mux on the Input and 1:2 Fan out on the output. Different input and output configuration can be selected. The following settings allow these different configurations: RAW FF //Select Channel Registers... - Page 11 RAW 31 //Allow register 0x03 to control CTLE setting RAW 3E //Restore initialization settings RAW 6A //Restore initialization settings RAW 2C //Disable VEO scale SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 12 4.2.8 Eye Opening Monitoring Operation The LMH0318 has an on-chip eye opening monitor (EOM) which can be used to analyze, monitor, and diagnose the performance of the link. The EOM operates on the post-equalized waveform, just prior to the data sampler. Therefore, it captures the effects of all the equalization circuits within the receiver.
- Page 13 Vertical Eye Opening (VEO) are indications of signal quality. These parameters can be read by the host processor or the LMH0318 can be optioned to cause interrupt if HEO/VEO reach a threshold. To convert the HEO reading to Unit Interval (UI) eye opening, we need to divide the HEO reading, in decimal, to 64.
- Page 14 OUT0 and OUT1 Mode Selection The LMH0318 75-Ω OUT0 and 50-Ω OUT1 can be configured to drive out the reclocked data, raw data (i.e non reclocked), clock, or these outputs to be muted (common mode voltage on both positive and negative output signal).
- Page 15 Device Configuration www.ti.com 4.2.11.2 OUT0 and OUT1 Independent Control: The LMH0318 allows independent control of OUT0 and OUT1. Note: 0x09[5] over-ride effects both OUT0 and OUT1. 4.2.11.2.1 OUT0 10 MHz Clock RAW FF //Select Channel Registers RAW 09 //Enable Over-ride...
- Page 16 RAW 1E //Invert OUT1 Polarity 4.2.13 OUT0 and OUT1 Settings The LMH0318 has programmable VOD (Voltage Output Differential), Pre-Emphasis (OUT0), PW (Pulse Width OUT0 settings), De-Emphasis Settings, and individual power-down settings LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback...
- Page 17 OUT1 De-Emphasis Settings There are 15 output de-emphasis settings for the LMH0318 OUT1, ranging from 0 dB to -11 dB. The de- emphasis values come from register 0x85, bits 2:0 and 0x85 bit 3, which is the de-emphasis range bit.
- Page 18 4.2.14 Signal Quality Alert HEO Interrupt Threshold The LMH0318 can be optioned to cause interrupt if HEO goes below certain threshold and reg 0x56[3] = 1'b. The LMH0318 compares HEO value, reg 0x27[7:0], vs threshold setting of reg 0x32[7:4]*4. Note: Register 0x54[7:0] indicates source of interrupt.
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Page 19: Register Tables
2. Receiver Registers: Equalizer boost settings and signal detect setting 3. CDR Registers: PLL control 4. Transmitter Registers: OUT0 and OUT1 parameter setting The typical device initialization sequence for the LMH0318 includes the followings. For detailed register settings See LMH0318 Programming Guide (SNLU183). 1. Shared Register Configuration... - Page 20 LOS1 1: Loss of signal on IN1 0: Signal present on IN1 LOS0 1: Loss of signal on IN0 0: Signal present on IN0 LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 21 1: IN1 Signal Detect loss interrupt 0: No interrupt from IN1 Signal Detect signal_det0_loss_int 1: IN0 Signal Detect loss interrupt 0: No interrupt from IN0 Signal Detect SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 22 IN1 signal_det0_loss_int_en 1: Enable interrupt if there is loss of signal on IN0 0: Disable interrupt if there is loss of signal on IN0 LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
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Page 23: Receiver Registers
0: Powers up EQ of the selected channel Reserved eq_en_bypass 1: Bypass stage 3 and 4 of CTLE 0: Enable Stage 3 and 4 of CTLE Reserved SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated... - Page 24 CTLE Mode of Operation and 0x00 Input/Output Mux Selection Reserved adapt_mode[1] 00: Normal Operation - Manual CTLE Setting adapt_mode[0] 01: Test Mode - See the LMH0318 Programming Guide (SNLU183) for details Other Settings - Invalid Reserved Reserved Reserved input_mux_ch_sel[1] IN0/1 and OUT0/1 selection...
- Page 25 I2_BST2[0] Index 2 Boost Stage 2 bit 0 I2_BST3[1] Index 2 Boost Stage 3 bit 1 I2_BST3[0] Index 2 Boost Stage 3 bit 0 SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 26 I7_BST2[0] Index 7 Boost Stage 2 bit 0 I7_BST3[1] Index 7 Boost Stage 3 bit 1 I7_BST3[0] Index 7 Boost Stage 3 bit 0 LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 27 I12_BST2[0] Index 12 Boost Stage 2 bit 0 I12_BST3[1] Index 12 Boost Stage 3 bit 1 I12_BST3[0] Index 12 Boost Stage 3 bit 0 SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 28 EQ Adaptation Control Reserved Reserved Reserved Reserved Reserved Reserved INIT_CDR_SM_4 At power-up, this bit needs to be set to 1'b. See initialization set up Reserved LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
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Page 29: Cdr Registers
00: 3.125 mV 01: 6.25 mV eom_sel_vrange[0] 10: 9.375 mV 11: 12.5 mV 0: EOM Operational eom_PD 1: Power down EOM Reserved Reserved Reserved Reserved Reserved SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated... - Page 30 0: Normal operation EOM_MSB Reg 0x25 Channel 0x00 Eye opening monitor hits(MSB) eom_count[15] eom_count[14] eom_count[13] eom_count[12] MSBs of EOM counter eom_count[11] eom_count[10] eom_count[9] eom_count[8] LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 31 EOM Vrange Readback Reserved eom_vrange_setting[1] Auto Vrange readback of eye monitor granularity 00: 3.125mV 01: 6.25mV eom_vrange_setting[0] 10: 9.375mV 11: 12.5mV Reserved Reserved Reserved Reserved Reserved SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 32 Compares HEO value, 0x27[7:0], vs threshold 0x32[7:4] * 4 heo_int_thresh[1] heo_int_thresh[0] veo_int_thresh[3] veo_int_thresh[2] Compares VEO value, 0x28[7:0], vs threshold 0x32[3:0 * 4 veo_int_thresh[1] veo_int_thresh[0] LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 33 0: Disable CDR Lock to 1.485/1.4835 Gbps 1: Enable CDR Lock to 2.97/2.967 Gbps 3G_enable 0: Disable CDR Lock to 2.97/2.967 Gbps Reserved Reserved Reserved Reserved SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
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Page 34: Transmitter Registers
0x1c[4] = 1 010: Full Rate Clock 001: Retimed Data 000: Raw Data Other Settings - Invalid Reserved Reserved Reserved Reserved Reserved LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated... - Page 35 1: Power down OUT1 driver 0: OUT1 in normal operating mode OUT1_DE Reg 0x85 0x00 OUT1 DE Control Reserved Reserved Reserved Reserved SNLU183 – September 2015 LMH0318 Programming Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 36 ADDRESS drv_1_dem_range Controls de-emphasis of 50 Ω Driver 0000: DE Disabled drv_1_dem[2] 0001: 0.2 dB drv_1_dem[1] 0010: 1.8 dB ..drv_1_dem[0] 0111: 11 dB LMH0318 Programming Guide SNLU183 – September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
- Page 37 STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions.
- Page 38 FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
- Page 39 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 2. 実験局の免許を取得後ご使用いただく。 3. 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page SPACER EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
- Page 40 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated...
- Page 41 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
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