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2.4. Schematics
Figure 4 is the schematics of WG1300E00 EM Board
The Antenna matching circuit.
ANT1
C1
AT8010-E2R9HAA
2.2pF
8.0x1.0x1.0mm
CAP1005
1
L1
L2
NL
2.2nH
IND1005
IND1005
To VIO_SYS Host Level
U2
VBAT_SY S
SN74AVC2T45
VIO_SYS: Voltage of Host Level
XBGA-N8_1X2_0.5-A
1
VCCA
VCCB
WL_SPI_CS_HOST
2
A1
3
-->
A2
4
GND
U4
VBAT_SY S
SN74AVC2T45
XBGA-N8_1X2_0.5-A
1
VCCA
VCCB
2
WL_SPI_DIN_HOST
A1
WL_SPI_CLK_HOST
3
-->
A2
4
GND
U5
VBAT_SY S
SN74AVC2T45
XBGA-N8_1X2_0.5-A
1
VCCA
VCCB
WL_SPI_IRQ_HOST
2
A1
3
WL_SPI_DOUT_HOST
A2
4
GND
Connect to Host SPI Interface.
DIR High : A data to B bus
(Host I/O level: VIO_SYS)
DIR Low : B data to A bus
EM Connector
1
2
3
4
5
6
32KHz_1V8_HOST
R20
NL_0R
7
8
RES1005
9
10
VBAT_SW_EN
11
12
WL_SPI_IRQ_HOST
13
14
WL_SPI_CS_HOST
15
16
WL_SPI_CLK_HOST
17
18
WL_SPI_DIN_HOST
19
20
WL_SPI_DOUT_HOST
J6
SFM-110-02-L-D-A
pitch 1.27-2x10
Figure 4. Schematics of WG1300BE00 EM Board
Copyright
R2
R3
0R
RES1005
0R
RES1005
U1
E_N51_14.5X14.5_1.3
VBAT_IN
WG1300-B0
J12
2
1
28
VBAT_IN
29
Male 1x2
GND
30
DC2DC_OUT
DC2DC_OUT
VIO_SOC
31
GND
32
R9
0R
RES1005
CLK_REQ_OUT
33
Networking Subsystem Debug
NS_UART
NS_UARTD
34
C2
GND
10pF
35
CAP1005
RF_ANT
J1
36
GND
U.FL-R-SMT(10)
U.FL
2
1
3
C3
NL_10pF
CAP1005
WL Debug Logger
VIO_SOC
J14
8
3
WL_EN1
2
WL_EN2
7
WL_SPI_CS_1V8
1
B1
6
B2
Male 1x3
5
VBAT_SY S
DIR
VIO_SOC
Debug mode => 1-2 short to GND
8
Functional mode => 2-3 short
7
WL_SPI_DIN_1V8
B1
6
WL_SPI_CLK_1V8
B2
5
DIR
VBAT_SY S
J13
6
5
DC2DC_OUT
4
NS_UART
VIO_SOC
3
WL_DBG
2
WL_TX
8
1
WL_RX
7
WL_SPI_IRQ_1V8
B1
Male 1x6
6
WL_SPI_DOUT_1V8
B2
5
DIR
VBAT_SY S
J10
2
1
2
1
3
4
5
6
7
8
Male 1x2
9
10
11
12
13
14
15
16
32KHz_1V8_HOST
R21
NL_0R
RES1005
17
18
19
20
J7
C22
SFM-110-02-L-D-A
10uF
pitch 1.27-2x10
CAP2012
©
JORJIN TECHNOLOGIES INC. 2014
http://WWW.JORJIN.COM.TW
CONFIDENTIAL
Doc No: WG1300BE00 EM Board-UG-R02
J16
NL_Male 1x3
18
GND
17
EXT_32K
16
GND
15
R8
0R
RES1005
SPI_CS
14
R10
0R
RES1005
SPI_CLK
13
R11
0R
RES1005
SPI_IRQ
12
R12
0R
RES1005
SPI_DOUT
11
R13
0R
RES1005
SPI_DIN
10
GND
Reserved VIO CLK LDO
VIO_SOC
RTTT Debug
J11
Male 1x2
WL_EN1
VBAT_SYS FET SWITCH
VBAT_SYS: 2.7V~4.8V => 3.6V TYP
VBAT_SY S
R19
NL_10K
C5
0.1uF
RES1005
CAP1005
VBAT_SW_EN
R17
RES1005
R18
Internal Power FET Switch Enable.
100K
RES1005
Connect to Host GPIO.
SLOW CLK 32.768KHz
OSC1
VIO_SOC
SG-3030LC/32.768kHz
CY -N12_3.6X2.8_0.5
R1
0R
RES1005
VBAT_IN
VIO_CLK
VBAT_SY S
R4
NL_0R
RES1005
R6
R22
NL_0R
0R
R5
RES1005
RES1005
0R
RES1005
32KHz_1V8_HOST
R7
NL_0R
RES1005
WL_SPI_CS_1V8
The 32.768kHz clock select.
Connect to OSC or Host source.
WL_SPI_CLK_1V8
WL_SPI_IRQ_1V8
WL_SPI_DOUT_1V8
WL_SPI_DIN_1V8
VIO_CLK:
3.3V
VIO_CLK
R16
NL_100K
RES1005
U7
CAP1608
NL_TPS79733
C7
VBAT_IN
VBAT_SY S
MO-203_2.1x2
NL_1uF
1
5
PG
OUT
2
R14
R23
GND
NL_0R
NL_0R
3
4
RES1005
RES1005
NC
IN
VIO LDO
VIO_SOC
VIO_SOC: 1.62V~1.92V => 1.8V TYP
R15
100K
RES1005
U3
CAP1608
TPS79718
C4
MO-203_2.1x2
1uF
1
5
PG
OUT
VBAT_IN
2
GND
3
4
NC
IN
VBAT_SY S
U6
VBAT_IN
TPS22913B
XBGA-N4_0.9x0.9_0.5
A2
A1
VIN
VOUT
B2
B1
0R
C6
ON
GND
1uF
CAP1608
Page 13
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