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DG FPGA Setup
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DG FPGA Setup

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dg_toe100gip_fpgasetup_xilinx.doc
FPGA setup for TOE100G-IP with CPU Demo
Rev1.1 28-Apr-21
1 Overview
This document describes how to setup FPGA board and prepare the test environment for running
TOE100G-IP demo. The user can setup two test environments for transferring TCP data via
100Gb Ethernet connection by using TOE100G-IP, as shown in Figure 1-1.
Figure 1-1 Two test environments for running the demo
28-Apr-21
Page 1

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Summary of Contents for DG FPGA

  • Page 1 Rev1.1 28-Apr-21 1 Overview This document describes how to setup FPGA board and prepare the test environment for running TOE100G-IP demo. The user can setup two test environments for transferring TCP data via 100Gb Ethernet connection by using TOE100G-IP, as shown in Figure 1-1.
  • Page 2 First uses one FPGA board and Test PC with 100Gb Ethernet card for transferring the data. TestPC runs test application to transfer data with TOE100G-IP on FPGA, tcpdatatest for half-duplex test or tcp_client_txrx_40G for full-duplex test. Also, Serial console or JTAGUART is run on Test PC to be user interface console.
  • Page 3 • USB cable for connecting between FPGA and PC a) KCU116: 2 micro USB cables for programming FPGA and Serial console b) U250 card: 1 micro USB cable for programming FPGA and Serial console c) FB2CGHH@KU15P card: 1 mini USB cable for programming FPGA and JTAGAURT •...
  • Page 4 Figure 2-1 TOE100G-IP with CPU demo (FPGA <-> PC) on KCU116 28-Apr-21 Page 4...
  • Page 5 Figure 2-2 TOE100G-IP with CPU demo (FPGA <-> PC) on U250 card 28-Apr-21 Page 5...
  • Page 6 Figure 2-3 TOE100G-IP with CPU demo (FPGA <-> PC) on FB2CGHH@KU15P 28-Apr-21 Page 6...
  • Page 7 The step to setup test environment by using FPGA and PC is described in more details as follows. 1) Connect USB cables between FPGA and PC for JTAG programming and Serial console/JTAGUART. a) For KCU116 board, connect two micro USB cables...
  • Page 8 3) Connect 100Gb Ethernet cable between FPGA board and PC. a) For KCU116, insert four SFP28 transceivers and MTP to 8xLC Fiber cable on FPGA board. Please check channel number of four cables to match with Figure 2-5. Figure 2-5 100Gb connection on KCU116 board by QSFP28 to 4xSFP28 cable...
  • Page 9 dg_toe100gip_fpgasetup_xilinx.doc b) For Alveo U250 and FB2CGHH@KU15P card, insert 100G QSFP28 Transceiver and MPO to MPO cable by using QSFP1 connector, as shown in Figure 2-6. Figure 2-6 100Gb connection on U250 card and FB2CGHH@KU15P card by QSFP28 transceiver and MPO to MPO cable 28-Apr-21 Page 9...
  • Page 10 6) For KCU116 and U250 card, open Serial console and download configuration file with firmware by following step. i) Open Serial console. When connecting FPGA board to PC, many COM ports from FPGA connection are detected and displayed on Device Manager.
  • Page 11 Download configuration file and firmware to FPGA board or accelerator card by using Vivado tool, as shown in Figure 2-8. Figure 2-8 Program FPGA by Vivado 28-Apr-21 Page 11...
  • Page 12 dg_toe100gip_fpgasetup_xilinx.doc 7) For FB2CGHH@KU15P card, open vivado TCL shell and browse to the directory that include batch file, bit file, and elf file of TOE100G demo. After that, run the test by typing following command. i) >> TOE100CPUTest_Silicom.bat Note: This step is to download configuration file and firmware, as shown in Figure 2-9. Figure 2-9 Command script to download demo file on Vivado TCL shel ii) >>...
  • Page 13 “dg_toe100gip_cpu_instruction” document. Figure 2-13 Initialization complete Note: Transfer performance in the demo is limited by Test PC performance in Test platform. The best performance can be achieved when the test is run by using FPGA-to-FPGA connection. 28-Apr-21 Page 13...
  • Page 14 3 Test environment setup when using two FPGAs Before running the test, please prepare following test environment. • Two FPGA development boards which can be the same board or different board: KCU116 board, Alveo U250 accelerator card, and FB2CGHH@KU15P card •...
  • Page 15 Figure 3-1 TOE100G-IP with CPU demo (FPGA<->FPGA) 28-Apr-21 Page 15...
  • Page 16 The step to setup test environment by using two FPGAs is described in more details as follows. Follow step 1) – 7) of topic 2 (Test environment setup when using FPGA and PC) to prepare FPGA board and SFP28/QSFP28 connection for running the demo. After two FPGA boards have been configured completely, Serial console/JTAG Terminal displays the menu to select Client mode, Server mode, or Fixed MAC mode.
  • Page 17 dg_toe100gip_fpgasetup_xilinx.doc 2) Input ‘x’ to use default parameters or other keys to change parameters. The parameters of Server mode must be set before Client mode. i) Set parameters on Server console. ii) Set parameters on Client console to start IP initialization by transferring ARP packet. iii) After finishing initialization process, “IP initialization complete”...
  • Page 18 dg_toe100gip_fpgasetup_xilinx.doc 4 Revision History Revision Date Description 25-Feb-21 Initial version release 28-Apr-21 Support Silicom FB2CGHH@KU15P card 28-Apr-21 Page 18...