Download
Share
Print this page
  1. Manuals
  2. Brands
  3. DG Manuals
  4. Computer Hardware
  5. FPGA
  6. Setup

DG FPGA Setup

Hide thumbs Also See for FPGA:

Advertisement

Quick Links

Download this manual
dg_nvmeip_fpgasetup_xilinx_en.doc
FPGA Setup for NVMe-IP (for Gen4)/
This document describes the FPGA and environment setup for running NVMe-IP, NVMe-IP for
Gen4, NVMeG3-IP, or NVMeG4-IP demo on FPGA development board by using the PCIe adapter
board (AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR, or customized AB18-PCIeX16 adapter
board) with NVMe SSD. User controls the test operation via Serial console.
1 Environment Requirement
To run the demo on FPGA development board, please prepare following environment.
1) Supported FPGA Development board:
NVMe-IP for Gen4: Alveo-U50
NVMe-IP
NVMeG3-IP
NVMeG4-IP
2) PC installing Xilinx programmer software (Vivado) and Serial console software such as
HyperTerminal or TeraTerm
3) The PCIe adapter board (AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR, or
customized AB18-PCIeX16 adapter board) provided by Design Gateway
https://dgway.com/ABseries_E.html
Note: Customized AB18-PCIeX16 adapter board is the AB18 board which needs to
modified by the user to use Alveo-U50 connecting with NVMe SSD via PCIe connector.
The details of the board modification are described in Topic 3 (Customized AB18 board).
4) Xilinx power adapter for FPGA board, except Alveo-U50
5) ATX power supply for AB18-PCIeX16 adapter board or Customized AB18 board for
Alveo-U50
6) NVMe SSD connecting with PCIe adapter board
7) USB cable for JTAG programming and Serial console
7-series board
UltraScale/UltraScale+ board
Alveo board
13-Sep-21
NVMeG3-IP/NVMeG4-IP demo
: AC701, ZC706, VC707, KCU105, KCU116, ZCU106, or VCU118
: KCU105, KCU116, ZCU102, ZCU106, or VCU118
: KCU116, ZCU102, ZCU106 or VCU118
: One micro USB cable and one mini USB cable
: Two USB cables
: Alveo programming cable with micro USB cable
Rev4.3
13-Sep-21
Page 1

Advertisement

loading
Need help?

Need help?

Do you have a question about the FPGA and is the answer not in the manual?

Questions and answers

Related Manuals for DG FPGA

Summary of Contents for DG FPGA

  • Page 1 13-Sep-21 This document describes the FPGA and environment setup for running NVMe-IP, NVMe-IP for Gen4, NVMeG3-IP, or NVMeG4-IP demo on FPGA development board by using the PCIe adapter board (AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR, or customized AB18-PCIeX16 adapter board) with NVMe SSD. User controls the test operation via Serial console.
  • Page 2 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-1 NVMe-IP demo environment setup on VC707 (PCIe Gen2) Figure 1-2 NVMe-IP demo environment setup on ZC706 (PCIe Gen2) 13-Sep-21 Page 2...
  • Page 3 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-3 NVMe-IP demo environment setup on AC701 (PCIe Gen2) 13-Sep-21 Page 3...
  • Page 4 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-4 NVMe-IP/NVMeG3-IP demo environment setup on KCU105 with AB18 (PCIe Gen3) Figure 1-5 NVMe-IP demo environment setup on KCU105 with AB17 (PCIe Gen3) 13-Sep-21 Page 4...
  • Page 5 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-6 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on KCU116 with AB18 (PCIe Gen3/Gen4) 13-Sep-21 Page 5...
  • Page 6 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-7 NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU102 with AB17 (PCIe Gen3/Gen4) 13-Sep-21 Page 6...
  • Page 7 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-8 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU106 with AB18 (PCIe Gen3/Gen4) 13-Sep-21 Page 7...
  • Page 8 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-9 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on ZCU106 with AB17 (PCIe Gen3/Gen4) 13-Sep-21 Page 8...
  • Page 9 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-10 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on VCU118 with AB18 (PCIe Gen3/Gen4) 13-Sep-21 Page 9...
  • Page 10 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-11 NVMe-IP/NVMeG3-IP/NVMeG4-IP demo environment setup on VCU118 with AB17 (PCIe Gen3/Gen4) 13-Sep-21 Page 10...
  • Page 11 dg_nvmeip_fpgasetup_xilinx_en.doc Figure 1-12 NVMe-IP for Gen4 demo environment setup on Alveo-U50 with customized AB18 (PCIe Gen4) Note: The modification details of customized AB18 for using with Alveo-U50 are described in Topic 3 (Customized AB18 board) 13-Sep-21 Page 11...

  • Page 12: Demo Setup

    dg_nvmeip_fpgasetup_xilinx_en.doc 2 Demo setup 1) Power off system. 2) Check DIP switch setting for JTAG configuration on Zynq board. • For ZC706 board, set SW11=all OFF to configure PS from JTAG and set SW4[1:2]=[OFF ON] to connect JTAG with USB-to-JTAG interface, as shown in Figure 2-1.
  • Page 13 Confirm that two mini jumpers are inserted at J5 connector on AB18. ii) Connect ATX power supply to AB board. iii) Connect PCIe connector on FPGA board/Alveo card to FPGA Side (A-side) and connect NVMe PCIe SSD to device side (B-Side) on AB board, as shown in Figure 2-3 Warning: Please confirm that the SSD is inserted in the correct side of AB18 (B-side, not A-side) before power on system.
  • Page 14 dg_nvmeip_fpgasetup_xilinx_en.doc AB17-M2FMC i) Connect M.2 NVMe SSD to Drive#1 M.2 connector on AB17-M2FMC. ii) Connect AB17-M2FMC to HPC/HPC1 connector on KCU105(J22), ZCU106(J5), ZCU102(J4), or HSPC on VCU118 (J22), as shown in Figure 2-4 Figure 2-4 Setup AB17-M2FMC connection 13-Sep-21 Page 14...
  • Page 15 dg_nvmeip_fpgasetup_xilinx_en.doc 4) Connect USB cables for JTAG programming and Serial console. a) For AC701/VC707/ZC706, connect micro USB cable for JTAG and mini USB cable for Serial console. b) For KCU105/KCU116/ZCU106/VCU118, connect two micro USB cables for JTAG and Serial console. Figure 2-5 USB cable connection c) For Alveo-U50, connect Alveo programming cable to Alveo-U50 board by using Ribbon cable and connect micro USB cable for JTAG and Serial console as shown in...
  • Page 16 5) Power on FPGA development board, adapter board, and ATX power supply for AB18. Figure 2-7 Turn on power switch on adapter board 13-Sep-21 Page 16...
  • Page 17 dg_nvmeip_fpgasetup_xilinx_en.doc 6) After connecting USB cables to PC, additional COM port is detected. For Ultrascale/Ultrascale+ board/Alveo card, many COM ports are detected. a) KCU105/KCU116/VCU118: Select Standard COM port b) ZCU106: Select the lowest number of the additional COM ports c) Alveo-U50: Select number#2 of the additional COM ports On Serial console, set Buad rate=115,200, Data=8-bit, Non-Parity, and Stop = 1, as shown in Figure 2-8.
  • Page 18 dg_nvmeip_fpgasetup_xilinx_en.doc 7) When using AB17-M2FMC connection on KCU105 or VCU118 board, user must set VADJ on FMC connector as following step. KCU105 board Open Serial console to connect with Enhanced COM port (Buad rate=115,200 Data=8 bit Non-Parity Stop=1). The console shows System Controller menu, as shown in Figure 2-9. To set VADJ of FMC to 1.8V, the following step is recommended.
  • Page 19 dg_nvmeip_fpgasetup_xilinx_en.doc VCU118 board Open SCUI.exe and run following step. Figure 2-10 Setting VADJ of FMC for VCU118 i) Select File->Change the System Controller Port. ii) Select COM port number which is Enhanced COM Port. iii) Click “OK” button to confirm the port. iv) Select FMC tab ->...
  • Page 20 8) Download and program configuration file and firmware to FPGA board. AC701, VC707, KCU105, KCU116, VCU118, and Alveo-U50 card Configure FPGA by using Vivado tool, as shown in Figure 2-11. Figure 2-11 Program FPGA by Vivado ZC706, ZCU106, and ZCU102 board Open Vivado TCL shell and run NVMeIPTest_xxx.bat, NVMeG3IPTest_xxx.bat, or...
  • Page 21 9) Check LED status on FPGA board. The description of LED is as follows. Note: There is no LED status when running on Alveo card. Table 2-1 LED Definition GPIO LED Normal operation Clock is not locked or reset button is pressed...
  • Page 22 AB18 to FPGA side (Alveo card) and device side (SSD card). The default mode connects only pin 2 and 3 to send the power to the device only because FPGA board has its own power supply. Alveo card does not have its own power supply, so it needs to receive power supply from AB18.

  • Page 23: Revision History

    dg_nvmeip_fpgasetup_xilinx_en.doc 4 Revision History Revision Date Description 2-Jun-16 Initial version release 29-Jun-20 Remove instruction from the document and include NVMeG3-IP 27-Aug-20 Support KCU116 22-Dec-20 Support NVMeG4-IP 13-Sep-21 Support NVMe-IP for Gen4 13-Sep-21 Page 23...