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DG FPGA Setup

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dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc
FPGA setup for 2-Ch RAID0 by NVMe-IP Demo
This document describes the FPGA and test environment setup for running 2-ch RAID0 by using
NVMe-IP, NVMeG3-IP, or NVMeG4-IP demo on FPGA development board by using the
AB17-M2FMC board or AB18-PCIeX16 board with Quad M.2 card for connecting with two M.2
NVMe SSDs. It is recommended to use the same SSD models for RAID0 operation to match SSD
characteristic. User controls test operation via Serial console.
1 Test Environment setup
To run the demo on FPGA development board, please prepare following environment.
1) FPGA development board
NVMe-IP
NVMeG3-IP
NVMeG4-IP
2) The adapter of M.2 SSD
a. AB17-M2FMC board
https://dgway.com/ABseries_E.html
b. AB18-PCIeX16 board and Quad M.2 card
https://dgway.com/ABseries_E.html
https://www.asrock.com/mb/spec/product.asp?Model=ULTRA%20QUAD%20M.2%20CA
RD
3) Two M.2 NVMe SSDs, inserting to M.2 connector on AB17/Quad M.2 card
4) For AB18 only, ATX power supply for PCIe adapter board
5) Xilinx power adapter for FPGA board
6) Two micro USB cables for programming FPGA and Serial console, connecting between
FPGA board and PC
7) PC installing Xilinx programmer software (Vivado) and Serial console software such as
TeraTerm and HyperTerminal
15-Jul-21
: KCU105 (AB17)
: ZCU106 (AB17), ZCU102 (AB17)
: ZCU106 (AB17), VCU118 (AB18 + Quad M.2 card)
Rev2.1
15-Jul-21
Page 1

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Summary of Contents for DG FPGA

  • Page 1 Rev2.1 15-Jul-21 This document describes the FPGA and test environment setup for running 2-ch RAID0 by using NVMe-IP, NVMeG3-IP, or NVMeG4-IP demo on FPGA development board by using the AB17-M2FMC board or AB18-PCIeX16 board with Quad M.2 card for connecting with two M.2 NVMe SSDs.
  • Page 2 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc Figure 1-1 NVMe-IP RAID0 demo setup by AB17 on KCU105 15-Jul-21 Page 2...
  • Page 3 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc Figure 1-2 NVMeG3-IP/NVMeG4-IP RAID0 demo setup by AB17 on ZCU106 15-Jul-21 Page 3...
  • Page 4 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc Figure 1-3 NVMeG3-IP RAID0 demo setup by AB17 on ZCU102 15-Jul-21 Page 4...
  • Page 5 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc Figure 1-4 NVMeG4-IP RAID0 demo setup by AB18 on VCU118 15-Jul-21 Page 5...
  • Page 6 2 FPGA board connection setup 1) Power off system. 2) Connect two M.2 NVMe SSD to AB17-M2FMC/Quad M.2 card a) For AB17, connect two M.2 NVMe SSDs to Drive#1 and #2 connector and then connect AB17-M2FMC to HPC on KCU105 (J22), HPC-1 on ZCU106 (J5), or HPC-0 on ZCU102 (J4), as shown in Figure 2-1.
  • Page 7 Confirm that two mini jumpers are inserted at J5 connector on AB18. After that, connect FPGA Side (A-side) on AB18 to PCIe connector on FPGA board and connect Hyper Quad M.2 NVMe SSD Card to device side (B-Side) on AB18, as shown in Figure 2-3.
  • Page 8 3) Connect two micro USB cables between FPGA board and PC for FPGA programming and Serial console as shown in Figure 2-4. Figure 2-4 USB cable connection 4) Turn on power switch of AB17/AB18, ATX power supply for AB18 (when using AB18), and FPGA development board as shown in Figure 2-5.
  • Page 9 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc 5) After connecting USB cables to PC, many COM ports are detected. In case of KCU105/VCU118, select Standard COM port. In case of ZCU106/ZCU102, select Interface 0 COM port. On Serial console, the setting is as follows. Set Buad rate=115,200, Data=8-bit, Non-Parity, and Stop = 1, as shown in Figure 2-6. Figure 2-6 Select COM port and set COM port 15-Jul-21 Page 9...
  • Page 10 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc 6) For KCU105 board by AB17, open Serial console to connect with Enhanced COM port (Buad rate=115,200 Data=8 bit Non-Parity Stop=1). The console shows System Controller menu, as shown in Figure 2-7. To set VADJ of FMC to 1.8V, the following step is recommended.
  • Page 11 7) Program configuration file to FPGA board. a) For KCU105/VCU118, open Vivado tool to download configuration file, as shown in Figure 2-8. Figure 2-8 Programmed by Vivado on KCU105/VCU118 b) For ZCU102 and ZCU106, open Vivado TCL shell and change directory to download or directory that batch file is located.
  • Page 12 8) Check LED status on FPGA board. The description of LED is as follows. Table 2-1 LED Definition GPIO LED Normal operation 1) PCIe Clock or system Clock is not locked. 2) Reset button is pressed. System is busy...
  • Page 13 dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc 10) Main menu is displayed in Serial console and ready to receive command. Figure 2-11 Main menu after RAID0 finishes initialization 15-Jul-21 Page 13...

  • Page 14: Revision History

    dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc 3 Revision History Revision Date Description 9-Oct-17 Initial version release 29-Jun-20 Remove demo instruction from the document and add NVMeG3-IP 15-Jul-21 Include NVMeG4-IP demo 15-Jul-21 Page 14...