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DG FPGA Setup
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DG FPGA Setup

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dg_toeudp25gip_fpgasetup_xilinx.doc
FPGA setup for TOE/UDP25G-IP with CPU Demo
Rev2.0 7-Jun-21
1 Overview
This document describes how to setup FPGA board and prepare the test environment for running
TOE25G-IP/UDP25G-IP demo. The user can setup two test environments for transferring
TCP/UDP data via 25Gb Ethernet connection by using TOE25G-IP/UDP25G-IP, as shown in
Figure 1-1.
Figure 1-1 Two test environments for running the demo
7-Jun-21
Page 1

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Summary of Contents for DG FPGA

  • Page 1 Rev2.0 7-Jun-21 1 Overview This document describes how to setup FPGA board and prepare the test environment for running TOE25G-IP/UDP25G-IP demo. The user can setup two test environments for transferring TCP/UDP data via 25Gb Ethernet connection by using TOE25G-IP/UDP25G-IP, as shown in Figure 1-1.
  • Page 2 Firstly, it uses one FPGA board and Test PC with 25Gb Ethernet card for transferring the data. TestPC runs test application, i.e., tcpdatatest (half-duplex test TOE25G-IP), tcp_client_txrx_40G (full-duplex test for TOE25G-IP), or udpdatatest (application test for UDP25G-IP). Also, Serial console/JTAG Terminal is run on Test PC to be user interface console.
  • Page 3 KCU116: 25G SFP28 Active Optical Cable (AOC). • USB cable for connecting between FPGA and PC a) VCU118 and KCU116 board: 2 micro USB cables for programming FPGA and Serial console b) FB2CGHH@KU15P card: 1 mini USB cable for programming FPGA and JTAGAURT •...
  • Page 4 Figure 2-1 TOE25G-IP/UDP25G-IP with CPU demo (FPGA <-> PC) on VCU118 7-Jun-21 Page 4...
  • Page 5 Figure 2-2 TOE25G-IP/UDP25G-IP with CPU demo (FPGA <-> PC) on KCU116 7-Jun-21 Page 5...
  • Page 6 Figure 2-3 TOE25G-IP/UDP25G-IP with CPU demo (FPGA <-> PC) on FB2CGHH@KU15P 7-Jun-21 Page 6...
  • Page 7 The step to setup test environment by using FPGA and PC is described in more details as follows. 1) Connect USB cables between FPGA and PC for JTAG programming and Serial console/JTAGUART. a) KCU116 and VCU118 board: Connect two micro USB cables b) FB2CGHH@KU15P card: Connect one mini USB cable 2) Connect power supply to FPGA development board/FPGA accelerator card.
  • Page 8 3) Connect 25Gb Ethernet cable between FPGA board and PC. a) VCU118 and FB2CGHH@KU15P: Insert QSFP28 to SFP28 cable by using QSFP1 connector on VCU118 and plug SFP28 no.1 to 25Gb Ethernet card on Test PC, as shown in Figure 2-5.
  • Page 9 6) KCU116 board and U250 Card: Open Serial console and download configuration file with firmware by following step. i) Open Serial console. When connecting FPGA board to PC, many COM ports from FPGA connection are detected and displayed on Device Manager. Select Standard COM port.
  • Page 10 dg_toeudp25gip_fpgasetup_xilinx.doc ii) Set programmable clock to 322.265625 MHz a) VCU118 board: Set by using “VCU118 SCUI” application as shown in Figure 2-8. Figure 2-8 Reference clock programming for VCU118 b) KCU116 board: Set by using “KCU116 – Board User Interface” application as shown in Figure 2-9.
  • Page 11 Download configuration file and firmware to FPGA board by using Vivado tool to program configuration file, as shown in Figure 2-10. Figure 2-10 Program FPGA by Vivado 7-Jun-21 Page 11...
  • Page 12 dg_toeudp25gip_fpgasetup_xilinx.doc 7) FB2CGHH@KU15P card: Open vivado TCL shell and browse to the directory that includes batch file, bit file, and elf file of the demo. After that, run the test by typing following command i) >> TOE25CPUTest_Silicom.bat/UDP25CPU_Silicom.bat Note: This step is to download configuration file and firmware, as shown in Figure 2-11 Figure 2-11 Command script to download demo file on Vivado TCL shel ii) >>...
  • Page 13 dg_toeudp25gip_fpgasetup_xilinx.doc 8) On Serial console/JTAG Terminal, welcome message is displayed. i) Input ‘0’ to start TOE25G-IP/UDP25G-IP initialization in client mode (asking PC MAC address by sending ARP request). ii) Default parameter in client mode is displayed on the console. Figure 2-13 Message after system boot-up If Ethernet connection has the problem which makes the linked down, the error message is displayed on the console instead of welcome message, as shown in Figure 2-14.
  • Page 14 “dg_udp25gip_cpu_instruction” document. Figure 2-15 Initialization complete Note: Transfer performance in the demo is limited by Test PC performance in Test platform. The best performance can be achieved when the test is run by using FPGA-to-FPGA connection. 7-Jun-21 Page 14...
  • Page 15 3 Test environment setup when using two FPGAs Before running the test, please prepare following test environment. • Two FPGA development boards which can be the same board or different board: KCU116, VCU118 board, and FB2CGHH@KU15P card • 25Gb Ethernet cable:...
  • Page 16 Figure 3-1 TOE25G-IP/UDP25G-IP with CPU demo (FPGA<->FPGA) 7-Jun-21 Page 16...
  • Page 17 The step to setup test environment by using two FPGAs is described in more details as follows. Follow step 1) – 7) of topic 2 (Test environment setup when using FPGA and PC) to prepare FPGA board and SFP28/QSFP28 connection for running the demo. After two FPGA boards have been configured completely, Serial console/JTAG Terminal displays the menu to select Client mode, Server mode, or Fixed MAC mode.
  • Page 18 dg_toeudp25gip_fpgasetup_xilinx.doc 2) Input ‘x’ to use default parameters or other keys to change parameters. The parameters of Server mode must be set before Client mode. When running TOE25G-IP, i) Set parameters on Server console (board#1 console). ii) Set parameters on Client console (board#2 console) to start IP initialization by transferring ARP packet.
  • Page 19 Set parameters on Server console (board#1 console). If user does not change the default parameters, input ‘x’ to skip parameter setting. ii) For Client mode, user must change target port number (Target->FPGA) to use same value as target port number (FPGA->Target).
  • Page 20 dg_toeudp25gip_fpgasetup_xilinx.doc 4 Revision History Revision Date Description 5-Aug-20 Initial version release 15-Sep-20 Add KCU116 7-Jun-21 Add UDP25G-IP 7-Jun-21 Page 20...