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A • Specifications
A.1 Technical Specification
Table A-1 Technical Specification
Features
Details
System or
Support for up to 7 peripheral slots (four
Peripheral slot
at 66 MHz)
PowerPC Processor
Freescale MC7448
System Controller
Marvell 'Discovery V' MV64560
L2 Cache
7448 = 1 MByte with ECC
Main Memory
Up to 1 GByte of DDR2 SDRAM with ECC
Flash Memory
Up to 256 MBytes
Non-volatile RAM
128 KBytes
Serial EEPROM
8 KBytes
Real-Time Clock
Time Of Day/Calendar
2 x 10/100BaseT ports or
Ethernet Interfaces
1 x 10/100/1000BaseT port
USB 2.0 Host Ports
OHCI/EHCI compliant
Serial ports
2 x RS232/422 ports
Discrete Digital I/O
4 bits, TTL-compatible
Timers
4 x 32-bit timers
Watchdog Timer
Programmable 32-bit timer
Elapsed Time
Quarter second resolution
Indicator
CompactPCI
32-bit, 33/66 MHz, 3.3 V signaling only (not
Interface
5 V tolerant)
64-bit/133 MHz PCI-X
PMC Site Interface
(not 5 V tolerant)
DMA Controllers
6
JTAG Interface
Rear I/O and test connector access
Front Panel
Single width CompactPCI
48 IMP2B 3U cPCI Single Board Computer
LINK
IMP2AJTAG Manual, publication number
Comments
IMP2B detects a backplane signal to configure in System Slot or Peripheral Slot
mode
Clocked at up to 1.4 GHz
Combines a memory controller, two PCI-X interfaces and a range of
communications peripherals on a single chip
Runs at core speed
Interfaces with the CPU via a 64-bit data bus running at 200 MHz
Interfaces with the CPU via a 16-bit data bus running at 133 MHz.
8 MBytes are allocated to Boot Flash and the remainder to User Flash
Non-volatile storage for data that must not be lost when power is removed
Provided on the I
2
C bus as an optional location for MV64560 configuration data
1 second resolution. No Battery Backup
MV64560 provides 1 or 2 Ethernet channels, accessed through the J2 connector
Individual, software enabled power controllers, 0.5 A each
MV64560 provides 2 serial channels, both software selectable to be RS232 or
RS422, asynchronous only
4 bits of GPIO, each bit being capable of generating an interrupt
Provided by the MV64560. 7.5 ns resolution. Ability to cascade two timers to
provide a 64-bit timer
Provided by the MV64560. 7.5 ns resolution. Two thresholds
Logs the total accumulated time the SBC has been powered, and the number of
power cycles
Compliant with PICMG 2.0, Rev 3.0 and conforms to the mechanical definitions
of VITA 30.1
Backwards compatible with PCI. Operates at 3.3 V signaling (VIO) only
Available in the MV64560 for efficiently moving large blocks of data
JTAG header provided for factory test and software debug purposes
(IMP2AJTAG adaptor card required for easy access)
Levels 1 to 5 and Level 9
IMP2AJTAG-0HH.
Publication No. IMP2B-0HH/5
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