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3.15.14 Semaphore Register – Offset 0x00000060
Table 3-22 Semaphore Register
Bits
15 to 0
The Semaphore register is used to control access to a shared resource. It should
contain the slot number of the board that currently has access. To gain access, a
board should:
1. Wait until the register contains zero.
2. Write in its slot number.
3. If it reads back its slot number, it can access the shared resource.
4. When the access is complete, the semaphore should be cleared to zero.
To provide some protection, the register may only be written to when zero or cleared
to zero. This means that a board cannot take control of the resource, by writing its
own slot identifier, without it first being released by the current owner.
3.16 General Purpose I/O Controller
Up to 4 lines of general purpose I/O are provided, accessible through the
J2
connector. Each pin can be configured as either an input or an output and its value
can be read or written as appropriate. Each pin may be assigned a polarity (either
active-high or active-low), which determines how the registers display its active
state.
Each input signal is capable of generating an interrupt to the MV64560 interrupt
controller. Each signal can be configured as level- or edge-sensitive and can be
masked as required. Edge-triggered interrupts are latched in the
register until cleared by software.
All signals power-up as active high inputs with their interrupt enable bits disabled.
Software must enable an on-card buffer before any GPIO lines can be used. See the
EPLD
A
Masked Interrupt Status
interrupts to allow software to quickly identify the cause of an interrupt.
The GPIO[0] line is used at start-up or reset as a Fast Start/Fast BIT/Full BIT selection
input, as follows:
GPIO[0] low = Fast Start (BIT skipped if Fast Start enabled) or Fast BIT selected.
GPIO[0] high (default) = Full BIT selected.
Fast Start is enabled by bit 7 of
Where GPIO[0] is not available, Fast Start/Fast BIT is not supported.
34 IMP2B 3U cPCI Single Board Computer
Mode
Description
Read/Write
Semaphore
Control Register
1, bit 13
register is provided, which shows only active, enabled
Notes
See below. Reset value = 0x0
Configuration Register
Interrupt Active
1.
Publication No. IMP2B-0HH/5
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