Table of Contents
Advertisement
www.ti.com
on top of each other on adjacent layers (do not route the sense leads through a high-current path).
4. Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be
routed away from the high current paths.
5. The PCB should have a ground plane (return) connected directly to the return of all components
through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per
capacitor for small-signal components). A star ground design approach is typically used to keep circuit
block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and
ground-bounce issues. A single ground plane for this design gives good results. With this small layout
and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
6. The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
SLUU321C – June 2008 – Revised June 2011
Submit Documentation Feedback
Copyright © 2008–2011, Texas Instruments Incorporated
bq24150/150A/151/151A/152 YFF EVM (HPA256)
PCB Layout Guideline
7
Advertisement
Table of Contents
