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PCB Layout Guideline
Operation Mode is Charger Mode. Uncheck Charge Current Termination. Check STAT Pin. Select
Battery Regulation Voltage to 4.20V.
Measure → V(J2(VBAT+, VBAT–)) = 4.2 ± 100mV
Observe → D1 is on.
3. Enable Load #2.
Measure → V(J2(VBAT+, VBAT–)) = 2.5 ± 100mV
Measure → Ichrg = 160mA ± 40mA
Measure → Iin = 93mA ± 5mA
4. Select Charge Current to 950mA, select Input Current Limit to 500mA.
Measure → Ichrg = 750mA ± 100mA
Measure → Iin = 475mA ± 25mA
5. Check Disable Charger. Turn off PS#1, turn off Load #2 and disconnect
2.4.2
Boost Function
1. Adjust PS#1 output to 3.7V and disable the output. Connect the PS#1 in series with a current meter
(multimeter) to J2 (BAT+, BAT–). Make sure a voltage meter is connected across J2 (BAT+, BAT–).
2. Set the Load #1 current to 200mA ± 20mA but disable the output. Connect the output of the Load #1 in
series with a current meter (multimeter) to J1 (DC+, DC–). Make sure a voltage meter is connected
across J1 (DC+, DC–). The setup is now like
Load
#1
USB
Cable
3. Turn on PS#1 output
4. Software setup: Change Operation Mode to Boost Mode.
Measure → V(J1(DC+, DC–))=5V ± 0.2V
5. Enable Load #1.
Measure → V(J1(DC+, DC–))=5V ± 0.2V
Measure → Iin = 330mA ± 40mA
Measure → Io = 200mA ± 20mA
3
PCB Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from input to PGND, should be
placed as close as possible to the IC.
2. The output inductor should be placed close to the IC and the output capacitor connected between the
inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin
through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper
layout to minimize high frequency current path loop is critical.
3. The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the
sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or
6
bq24150/150A/151/151A/152 YFF EVM (HPA256)
BQ2415x
EVM
J 1
I
Io
APPLICATION
DC+
V
DC -
JMP1
D1
Ribbon
HPA172
Cable
J5
J3
Figure 4. Test setup for HPA256
Copyright © 2008–2011, Texas Instruments Incorporated
Figure 4
for HPA256.
J2
BAT+
JMP3
U1
AUXPWR
CD
BAT -
JMP5
CIRCUIT
JMP2
JMP4
J4
SLUU321C – June 2008 – Revised June 2011
www.ti.com
I in
I
Power
V
supply #1
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