Post Codes - Acer Aspire 4743Z Service Manual

POST Codes

The following table details the core POST codes and functions used in SecureCore.
Table 4-4. POST Codes
POST Code
0xE3 First Legacy BIOS Task table for legacy reset
0x20 Verify that DRAM refresh is operating by polling the refresh
bit in PORTB.
0xDA Dummy PCIE Init entry, now handled by driver
0x29 PMM (Post Memory Manager) Init
0xE5 WHEA Init
0x33 PDM (Post Dispatcher Manager) Init
0x01 IPMI Init
0xD8 ASF Init
0x09 Set in-POST flag in CMOS that indicates we are in POST.
If this bit is cleared by postClearBootFlagJ (AEh), the
TrustedCore on next boot determines that the current
configuration caused POST to fail and uses default values
for configuration.
0x2B Enhanced CMOS
0XE0 EFI Variable Init
0xC1 PEM (Post Error Manager) Init
0x3B Debug Service Init (ROM Polit)
0xDC POST Update Error
0x3A Autosize external cache and program cache size for
enabling later in POST.
0x0B Enable CPU cache. Set bits in CMOS related to cache.
0x0F Enable the local bus IDE as primary or secondary
0x10 Initialize Power Management
0x14 Verify that the 8742 keyboard controller is responding.
Send a self-test command to the 8742 and wait for results.
Also read the switch inputs from the 8742 and write the
keyboard controller command byte.
4-26
Function Phase Component
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
LBT Core
Troubleshooting
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