Circuit Diagram (Main Board: Power) - Boss GT-100 Service Notes

Mar. 2012

Circuit Diagram (Main Board: Power)

fig.d-main-1.eps@L
JK1
2
3
DC IN
1
5
4
KM02018ABM1P
CN2 CN2
DR-670 DC JACK HOLDER(G2147127)
FB+14V
GND
28
PUSH(>100ms) POWER ON
L7
D2
SS3003CH-TL-E
SS11VL-17024
4
4 1
3
NC
3 2
FB+1.2V
FB+3.3V
FB-14V
R106 10k
D ( 0.5% )
TP261
D+3.3
1SS387(TPH3.F)
D5
R62 R61
10k 10k
1608
1608
TP405
11
12 13 2
Q7
DTA114TUAT106
21
22 23
SW1 SPUP192000
D6
SW1 SPUP192000
1SS361FV(TPL3.Z)
1
TP23
GND
TP16
4
S
R90
33k
1
1608
2
5 TP33 1
6
R102
10k
1608
TP32
TP404
Q6
DTC114EUAT106(PB FREE)
C45 UnPop
R68 2.2k
C144 6800pF
TP256 TP257
C284 UnPop
R75 3.9k
C74 4700pF
TP252 TP254
R63 47k
C286 UnPop
R69 2.2k R316 1.2k
C73 1000pF C283 2200pF
TP262 TP263 TP29 TP203
C285 UnPop
R65 12k
C75 1500pF
TP265 TP266
PVCC
1
TP28
XSYS-RST
TP65
GND
GT-100
D1
1SS362FV(TPL3)
2 1
To CPU
R86
UnPop
GND
XSWD-PWR
R72 1k
1005
GND
From CPU
H->POWER ON
L->POWER OFF
2
XPWR-OFF
PVCC
Q10
MCH6306-TL-E
6
D4
5
D3
2
D2
1
D1
C146
C20
470uF
0.1uF
16V
1
GND
C108 10uF
2125
C29
0.1uF
C56
0.1uF
GND
38 35
-INE1 OUT1-1
37 34
FB1 OUT1-2
TP409
39
CS1
C31 0.015uF
41 33
-INE2 OUT2
42
FB2
TP410
40
CS2
C30 0.015uF
43
DTC2
46 32
-INE3 OUT3
45
FB3
47
CS3
44
DTC3
19 31
-INA OUT4
18
OUTA
16
-INE4
15
FB4
TP407
17
CS4
C55 0.1uF
14
DTC4
21
-INE5
22
FB5
30
TP406
OUT5
20
CS5
C186 0.1uF
23
DTC5
26
-INE6
25
FB6
29
OUT6
27
CS6
24
DTC6
TP115
9
VREF
C282 0.1uF
8 11
TP202 -INS RT
13 12
CSCP CT
C67 0.47uF
tscp = 0.33 sec.
2
CTL1
3
CTL2
4
CTL3
5
CTL4
6
CTL5
7
CTL6
1
CTL
IC2
MB39A123PMT-G-JN-EFE1
fOSC=1.00MHz
GND
GND
TP223
TP244
TP221
TP220