ECS P6VPA2 Manual page 53

DRAM Clock/Drive Control
Scroll to DRAM Clock/Drive Control and press <Enter> to view the
following screen:
CMOS Setup Utility – Copyright © 1984 – 2000 Award Software
Current FSB Frequency
DRAM Clock
DRAM Timing
x SDRAM Cycle Length
x Bank Interleave
↑ ↓ → ← : Move Enter : Select
F5:Previous Values
Current FSB Frequency
This is a display only field that shows the frontside bus frequency.
DRAM Clock
This item sets the DRAM Clock. We recommend that you leave this
item at the default value.
DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
timings programmed into this register are dependent on the system
design. Slower rates may be required in certain system designs to
support loose layouts or slower memory. When set to manual, the
following two items become available:
•
SDRAM Cycle Length: This item sets the timing and wait
states for SDRAM memory. We recommend that you leave
this item at the default value.
•
Bank Interleave: Enable this item to increase memory speed.
When enabled, separate memory banks are set for odd and
even addresses and the next byte of memory can be accessed
while the current byte is being refreshed.
After you have made your changes in the DRAM Clock/Drive Control
screen, press <Esc> to return to the Advanced Chipset Features screen.
DRAM Clock/Drive Control
Host CLK
By SPD
3
DRAM Clock
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
47
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults
Default: Host CLK
Default: By SPD