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SiFive FE310-G000 Manual

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  • Page 1 SiFive FE310-G000 Manual v3p2 © SiFive, Inc.
  • Page 2 SiFive does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, spe- cial, exemplary, or consequential damages.
  • Page 3 1.0.3 July 24, 2017 assignments 1.0.2 June 12, 2017 Clarify that QFN48 is the 6x6 Standard format • Add QFN48 Package Pinout 1.0.1 December 20, 2016 • Add Configuration String • Rename chip to FE310-G000 November 29, 2016 HiFive1 release...

  • Page 4: Table Of Contents

    Memory Map ......................18 Boot Process ......................20 ..................20 Non-volatile Code Options ..................20 5.1.1 Gate ROM (GROM) ..................20 5.1.2 Mask ROM (MROM) ............21 5.1.3 One-Time Programmable (OTP) Memory SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 1...
  • Page 5 Machine Trap Vector (mtvec) .................36 8.3.3 Machine Interrupt Enable (mie) ...............37 8.3.4 Machine Interrupt Pending (mip) ................. 38 8.3.5 Machine Cause (mcause) ..................... 39 Interrupt Priorities ....................... 39 Interrupt Latency Core-Local Interruptor (CLINT) ..............40 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 2...
  • Page 6 Reset Cause ................... 55 12.6 Watchdog Timer (WDT) .................... 55 12.7 Real-Time Clock (RTC) ....................55 12.8 Backup Registers ................55 12.9 Power-Management Unit (PMU) ....................55 12.10 AON Memory Map SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 3...
  • Page 7 15.2 RTC Configuration Register (rtccfg) ................70 15.3 RTC Compare Register (rtccmp) General Purpose Input/Output Controller (GPIO) ......71 ................. 73 16.1 GPIO Instance in FE310-G000 ......................73 16.2 Memory Map ....................74 16.3 Input / Output Values ........................ 74 16.4 Interrupts .....................
  • Page 8 16.8 HW I/O Functions (IOF) Universal Asynchronous Receiver/Transmitter (UART) ....76 ...................... 76 17.1 UART Overview ................76 17.2 UART Instances in FE310-G000 ......................77 17.3 Memory Map ................77 17.4 Transmit Data Register (txdata) ................78 17.5 Receive Data Register (rxdata) .................78...
  • Page 9 ....................... 94 19.1 PWM Overview ................95 19.2 PWM Instances in FE310-G000 ....................95 19.3 PWM Memory Map ................96 19.4 PWM Count Register (pwmcount) ..............97 19.5 PWM Configuration Register (pwmcfg) .................98 19.6 Scaled PWM Count Register (pwms) ............99 19.7 PWM Compare Registers (pwmcmp0–pwmcmp3) ...................
  • Page 10 .................... 113 21.2 Resetting JTAG Logic ...................... 113 21.3 JTAG Clocking ................... 114 21.4 JTAG Standard Instructions ..................114 21.5 JTAG Debug Commands References ......................115 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 7...

  • Page 11: Introduction

    Chapter 1 Introduction The FE310-G000 is the first Freedom E300 SoC, and forms the basis of the HiFive1 develop- ment board for the Freedom E300 family. The FE310-G000 is built around the E31 Core Com- plex instantiated in the Freedom E300 platform and fabricated in the TSMC CL018G 180nm process.
  • Page 12 Watchdog psdlfaltclk Real-Time Clock Ticks LFROSC psdlfaltclksel erst_n Reset Unit Figure 1: FE310-G000 top-level block diagram. Table 1: FE310-G000 Feature Summary. Available in Feature Description QFN48 1× E31 RISC‑V cores with machine mode only, 16 KiB ✔ RISC-V Core 2-way L1 I-cache, and 16 KiB data tightly integrated mem- ory (DTIM).

  • Page 13: E31 Risc-V Core

    1.3 Interrupts The FE310-G000 includes a RISC-V standard platform-level interrupt controller (PLIC), which supports 51 global interrupts with 7 priority levels. The FE310-G000 also provides the standard RISC‑V machine-mode timer and software interrupts via the Core-Local Interruptor (CLINT). Interrupts are described in Chapter 8. The CLINT is described in Chapter 9. The PLIC is described in Chapter 10.

  • Page 14: Gpio Complex

    1.8 Hardware Serial Peripheral Interface (SPI) There are 3 serial peripheral interface (SPI) controllers. Each controller provides a means for serial communication between the FE310-G000 and off-chip devices, like quad-SPI Flash mem- ory. Each controller supports master-only operation over single-lane, dual-lane, and quad-lane protocols.
  • Page 15 Chapter 1 Introduction Debug support is described in detail in Chapter 20, and the debug interface is described in Chapter 21. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 12...

  • Page 16: List Of Abbreviations And Terms

    Joint Test Action Group JTAG Loosely Integrated Memory. Used to describe memory space delivered in a SiFive Core Complex but not tightly integrated to a CPU core. Physical Memory Protection Platform-Level Interrupt Controller. The global interrupt controller in a PLIC RISC-V system.
  • Page 17 Writes-Preserve Reads-Ignore field. A register field that might contain WPRI unknown information. Reads should ignore the value returned, but writes to the whole register should preserve the original value. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 14...

  • Page 18: E31 Risc-V Core

    Chapter 3 E31 RISC-V Core This chapter describes the 32-bit E31 RISC‑V processor core used in the FE310-G000. The E31 processor core comprises an instruction memory system, an instruction fetch unit, an exe- cution pipeline, a data memory system, and support for global, software, and timer interrupts.

  • Page 19: Instruction Fetch Unit

    Branch and jump instructions transfer control from the memory access pipeline stage. Correctly- predicted branches and jumps incur no penalty, whereas mispredicted branches and jumps incur a three-cycle penalty. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 16...

  • Page 20: Data Memory System

    See The RISC‑V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1 for more infor- mation on the instructions added by this extension. 3.6 Hardware Performance Monitor The FE310-G000 supports a basic hardware performance monitoring facility compliant with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. The mcycle CSR holds a count of the number of clock cycles the hart has executed since some arbitrary time in the past.

  • Page 21: Memory Map

    Chapter 4 Memory Map The memory map of the FE310-G000 is shown in Table 3. Table 3: FE310-G000 Memory Map. Memory Attributes: R - Read, W - Write, X - Execute, C - Cacheable, A - Atomics Base Attr. Description...
  • Page 22 Chapter 4 Memory Map Table 3: FE310-G000 Memory Map. Memory Attributes: R - Read, W - Write, X - Execute, C - Cacheable, A - Atomics Base Attr. Description Notes QSPI 0 Control 0x1001_4000 0x1001_4FFF PWM 0 0x1001_5000 0x1001_5FFF Reserved...

  • Page 23: Boot Process

    RAM. The debug RAM code can be used to bootstrap download of further code. 5.1.2 Mask ROM (MROM) MROM is fixed at design time, and is located on the peripheral bus on FE310-G000, but instruc- tions fetched from MROM are cached by the core’s I-cache. The MROM contains an instruction at address...

  • Page 24: One-Time Programmable (Otp) Memory

    Off-chip SPI devices can vary in number of supported I/O bits (1, 2, or 4). SPI flash bits contain all 1s prior to programming. 5.2 Reset and Trap Vectors FE310-G000 fetches the first instruction out of reset from . The instruction stored there 0x1000...

  • Page 25: Clock Generation

    AON block (Chapter 12) or the PRCI block (Section 6.2). 6.1 Clock Generation Overview Figure 2: FE310-G000 clock generation scheme Figure 2 shows an overview of the FE310-G000 clock generation scheme. Most digital clocks on the chip are divided down from a central high-frequency clock produced from either hfclk the PLL or an on-chip trimmable oscillator.

  • Page 26: Prci Address Space Usage

    The AON block contains registers with similar func- tions, but only for the AON block units. Table 4 shows the memory map for the PRCI on the FE310-G000. Table 4: SiFive PRCI memory map, offsets relative to PRCI base address.

  • Page 27: External 16 Mhz Crystal Oscillator (Hfxosc)

    An external high-frequency 16 MHz crystal oscillator can be used to provide a precise clock source. The crystal oscillator should have a capacitive load of ≤ 12 pF and an ESR ≤ 80 Ω. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc.

  • Page 28: Internal High-Frequency Pll (Hfpll)

    The format of is shown in Table 7. pllcfg Table 7: pllcfg: PLL Configuration and Status pllcfg: PLL Configuration and Status ( pllcfg Register Offset Bits Field Name Attr. Rst. Description SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 25...
  • Page 29 Figure 3: Controlling the FE310-G000 PLL output frequency. field encodes the reference clock divide ratio as a 2-bit binary value, where the pllr[1:0] value is one less than the divide ratio (i.e., =4).
  • Page 30 The supply filter should be a 100 Ω resistor in series with the board 1.8 V supply decoupled with a 100 nF capacitor across the VDDPLL/VSSPLL supply pins. The VSSPLL pin should not be connected to board VSS. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 27...

  • Page 31: Pll Output Divider

    The LFROSC can be calibrated in software using a more accurate high-frequency clock source. Table 10: lfrosccfg: Ring Oscillator Configuration and Status lfrosccfg: Ring Oscillator Configuration and Status ( lfrosccfg 0x70 Register Offset Bits Field Name Attr. Rst. Description SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 28...

  • Page 32: Alternate Low-Frequency Clock (Lfaltclk)

    This mux selection can only be controlled by external pads, it is not psdlfaltclksel controllable by software. 6.9 Clock Summary Table 11 summarizes the major clocks on the FE310-G000 and their initial reset conditions. At power-on reset, the AON domain is clocked by either the LFROSC or , as...
  • Page 33 Chapter 6 Clock Generation Table 11: FE310-G000 Clock Sources 0.375 MHz 384 MHz hfclkrst JTAG TCK 0 MHz 16 MHz SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 30...

  • Page 34: Power Modes

    Chapter 7 Power Modes This chapter describes the different power modes available on the FE310-G000. The FE310-G000 supports three power modes: Run, Wait, and Sleep. 7.1 Run Mode Run mode corresponds to regular execution where the processor is running. Power consump- tion can be adjusted by varying the clock frequency of the processor and peripheral bus, and by enabling or disabling individual peripheral blocks.
  • Page 35 HFROSC at the default setting, and must reconfigure clocks to run from an alternate clock source (HFXOSC or PLL) or at a different setting on the HFROSC. Because the FE310-G000 has no internal power regulator, the PMU’s control of the power sup- plies is through chip outputs, .

  • Page 36: Interrupts

    Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 8.1 Interrupt Concepts The FE310-G000 supports Machine Mode interrupts. It also has support for the following types of RISC‑V interrupts: local and global. Local interrupts are signaled directly to an individual hart with a dedicated interrupt value. This...

  • Page 37: Interrupt Operation

    Chapter 8 Interrupts Figure 4: FE310-G000 Interrupt Architecture Block Diagram. 8.2 Interrupt Operation If the global interrupt-enable is clear, then no interrupts will be taken. If mstatus.MIE is set, then pending-enabled interrupts at a higher interrupt level will preempt cur- mstatus.MIE...

  • Page 38: Interrupt Control Status Registers

    A summary of the fields related to interrupts in mstatus the FE310-G000 is provided in Table 12. Note that this is not a complete description of mstatus as it contains fields unrelated to interrupts. For the full description of...

  • Page 39: Machine Trap Vector (Mtvec)

    FE310-G000 will process interrupts. The interrupt processing mode is defined in the lower two bits of the register as described in Table 14.

  • Page 40: Machine Interrupt Pending (Mip)

    Field Name Attr. Description [2:0] Reserved WIRI MSIP Machine Software Interrupt Pending [6:4] Reserved WIRI MTIP Machine Timer Interrupt Pending [10:8] Reserved WIRI MEIP Machine External Interrupt Pending [31:12] Reserved WIRI SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 37...

  • Page 41: Machine Cause (Mcause)

    Interrupt Exception Codes Interrupt Exception Code Description 0–2 Reserved Machine software interrupt 4–6 Reserved Machine timer interrupt 8–10 Reserved Machine external interrupt ≥ 12 Reserved Instruction address misaligned Instruction access fault Illegal instruction SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 38...

  • Page 42: Interrupt Priorities

    • Machine timer interrupts 8.5 Interrupt Latency Interrupt latency for the FE310-G000 is 4 cycles, as counted by the numbers of cycles it takes from signaling of the interrupt to the hart to the first instruction fetch of the handler.

  • Page 43: Core-Local Interruptor (Clint)

    Chapter 9 Core-Local Interruptor (CLINT) The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. The FE310-G000 CLINT complies with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 9.1 CLINT Memory Map Table 19 shows the memory map for CLINT on SiFive FE310-G000.

  • Page 44: Msip Registers

    The timer interrupt is reflected in the bit of the mtimecmp mtip register described in Chapter 8. On reset, is cleared to zero. The registers are not reset. mtime mtimecmp SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 41...

  • Page 45: Platform-Level Interrupt Controller (Plic)

    Architecture, Version 1.10 and supports 51 interrupt sources with 7 priority levels. 10.1 Memory Map The memory map for the FE310-G000 PLIC control registers is shown in Table 20. The PLIC memory map has been designed to only require naturally aligned 32-bit memory accesses.

  • Page 46: Interrupt Sources

    0x1000_0000 10.2 Interrupt Sources The FE310-G000 has 51 interrupt sources. These are driven by various on-chip devices as listed in Table 21. These signals are positive-level triggered. In the PLIC, as specified in The RISC‑V Instruction Set Manual, Volume II: Privileged Architec- ture, Version 1.10, Global Interrupt ID 0 is defined to mean "no interrupt."...

  • Page 47: Interrupt Priorities

    10.3 Interrupt Priorities Each PLIC interrupt source can be assigned a priority by writing to its 32-bit memory-mapped register. The FE310-G000 supports 7 levels of priority. A priority value of 0 is priority reserved to mean "never interrupt" and effectively disables the interrupt. Priority 1 is the lowest active priority, and priority 7 is the highest.

  • Page 48: Interrupt Enables

    Bit 0 of enable word 0 represents the non-existent interrupt ID 0 pending and is hardwired to 0. Only 32-bit word accesses are supported by the array in SiFive RV32 systems. enables SiFive FE310-G000 Manual: v3p2 © SiFive, Inc.

  • Page 49: Priority Thresholds

    WARL field, where the FE310-G000 supports a maximum threshold of 7. threshold The FE310-G000 masks all PLIC interrupts of a priority less than or equal to . For threshold example, a value of zero permits all interrupts with non-zero priority, whereas a threshold value of 7 masks all interrupts.

  • Page 50: Interrupt Claim Process

    (Table 28), which returns the ID of the highest-priority pending interrupt or zero if there is no pending interrupt. A successful claim also atomically clears the corresponding pending bit on the interrupt source. A FE310-G000 hart can perform a claim at any time, even if the MEIP bit in its (Table 16) register is not set.
  • Page 51 Complete for Hart rupts are pending. A non-zero read 0 M-Mode contains the id of the highest pending interrupt. A write to this register signals completion of the interrupt id written. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 48...

  • Page 52: One-Time Programmable Memory (Otp) Peripheral

    Name Description Programmed-I/O lock register 0x00 otp_lock OTP device clock signals 0x04 otp_ck OTP device output-enable signal 0x08 otp_oe OTP device chip-select signal 0x0C otp_sel OTP device write-enable signal 0x10 otp_we SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 49...

  • Page 53: Programmed-I/O Lock Register (Otp_Lock)

    Listing 1: Sequence to acquire and release otp_lock la t0, otp_lock li t1, 1 loop: sw t1, (t0) lw t2, (t0) beqz t2, loop # Programmed I/O sequence goes here. sw x0, (t0) SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 50...

  • Page 54: Programmed-I/O Sequencing

    OTP read sequencer control ( otp_rsctrl 0x34 Register Offset Bits Field Name Attr. Rst. Description [2:0] OTP timescale scale Address setup time Read pulse time Read access time tacc [31:6] Reserved SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 51...

  • Page 55: Otp Programming Warnings

    7. SOAK any verification failures by repeating steps 2-5 using 400 us pulses. 8. REVERIFY the rewritten bits setting =0xF. Steps 7,8 may be repeated up to otp_mrr 10 times before failing the part. 9. UNLOCK the otp by writing 0x0 to otp_lock SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 52...

  • Page 56: Always-On (Aon) Domain

    Chapter 12 Always-On (AON) Domain The FE310-G000 supports an always-on (AON) domain that includes real-time counter, a watchdog timer, backup registers, low frequency clocking, and reset and power-management circuitry for the rest of the system. Figure 5 shows an overview of the AON block.

  • Page 57: Aon Power Source

    12.3 AON Reset Unit An AON reset is the widest reset on the FE310-G000, and resets all state except for the JTAG debug interface. An AON reset can be triggered by an external active-low reset pin ( ), or expiration of the...

  • Page 58: Reset Cause

    The Real-Time Clock is described in detail in Chapter 15. 12.8 Backup Registers The backup registers provide a place to store critical data during sleep. The FE310-G000 has 16 32-bit backup registers. 12.9 Power-Management Unit (PMU) The power-management unit (PMU) sequences the system power supplies and reset signals when transitioning into and out of sleep mode.
  • Page 59 Backup Register 12 0x0B0 backup_12 Backup Register 13 0x0B4 backup_13 Backup Register 14 0x0B8 backup_14 Backup Register 15 0x0BC backup_15 Wakeup program instruction 0 0x100 pmuwakeupi0 Wakeup program instruction 1 0x104 pmuwakeupi1 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 56...
  • Page 60 Sleep program instruction 7 0x13C pmusleepi7 PMU Interrupt Enables 0x140 pmuie PMU Wakeup Cause 0x144 pmucause Initiate PMU Sleep Sequence 0x148 pmusleep PMU Key. Reads as 1 when PMU is unlocked 0x14C pmukey SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 57...

  • Page 61: Watchdog Timer (Wdt)

    The WDT is based around a 31-bit counter held in . The counter can be read wdogcount[30:0] or written over the TileLink bus. Bit 31 of returns a zero when read. wdogcount SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 58...

  • Page 62: Watchdog Clock Selection

    The WDT uses the signal from the wakeup sequencer to know when the corerst SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 59...

  • Page 63: Watchdog Compare Register (Wdogcmp)

    To prevent spurious reset of the WDT, all writes to wdogkey must be preceded by an wdogcfg wdogfeed wdogcount wdogcount wdogcmp wdogip0 unlock operation to the register location, which sets . The value wdogkey wdogkey 0x51F15E SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 60...

  • Page 64: Watchdog Feed Address (Wdogfeed)

    The register resides in the register, and can be read wdogip wdogcfg and written over TileLink to clear down the interrupt. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 61...

  • Page 65: Power-Management Unit (Pmu)

    Chapter 14 Power-Management Unit (PMU) The FE310-G000 power-management unit (PMU) is implemented within the AON domain and sequences the system’s power supplies and reset signals during power-on reset and when tran- sitioning the "mostly off" (MOFF) block into and out of sleep mode.

  • Page 66: Pmu Overview

    Signal Condition/ Synchronize Figure 7: FE310-G000 Power-Management Unit The PMU is a synchronous unit clocked by the in the AON domain. The PMU handles lfClk reset, wakeup, and sleep actions initiated by power-on reset, wakeup events, and sleep requests.

  • Page 67: Pmu Key Register (Pmukey)

    PMU register. The state bit is reset at AON reset, and after any write to a PMU register. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 64...

  • Page 68: Pmu Program

    Table 36: Default PMU wakeup program Program Instruction Value Meaning 0x1F0 Assert all resets and enable all power supplies 0x1F8 Idle cycles, then deassert hfclkrst 0x030 Deassert corerst padrst 0x030 Repeats SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 65...

  • Page 69: Initiate Sleep Sequence Register (Pmusleep)

    RTC comparator can rouse MOFF. Table 38: pmuie: PMU Interrupt Enables pmuie: PMU Interrupt Enables ( pmuie 0x140 Register Offset Bits Field Name Attr. Rst. Description [3:0] PMU Interrupt Enables pmuie [31:4] Reserved SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 66...
  • Page 70 PMU Wakeup Cause pmucause Table 40: Wakeup cause values Index Meaning Reset RTC Wakup ( Digitial input wakeup ( dwakeup Table 41: Reset cause values Index Meaning External reset Watchdog timer reset SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 67...

  • Page 71: Real-Time Clock (Rtc)

    ≥48-bit counter width ensures there will no counter rollover for over 270 years assuming a 32.768 kHz low-frequency real-time clock source. The counter registers can be read or written over the TileLink bus. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 68...

  • Page 72: Rtc Configuration Register (Rtccfg)

    . The maximum value of 15 in corresponds to rtcs rtclo rtcscale dividing the clock rate by , so for an input clock of 32.768 kHz, the LSB of will incre- rtcs SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 69...

  • Page 73: Rtc Compare Register (Rtccmp)

    Table 45: rtccmp0: Comparator 0 rtccmp0: Comparator 0 ( rtccmp0 0x60 Register Offset Bits Field Name Attr. Rst. Description [31:0] Comparator 0 rtccmp0 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 70...

  • Page 74: General Purpose Input/Output Controller (Gpio)

    This chapter describes the operation of the General Purpose Input/Output Controller (GPIO) on the FE310-G000. The GPIO controller is a peripheral device mapped in the internal memory map. It is responsible for low-level configuration of actual GPIO pads on the device (direction, pull up-enable, and drive value ), as well as selecting between various sources of the controls for these signals.
  • Page 75 Chapter 16 General Purpose Input/Output Controller Figure 9: Structure of a single GPIO Pin with Control Registers. This structure is repeated for each pin. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 72...

  • Page 76: Gpio Instance In Fe310-G000

    Chapter 16 General Purpose Input/Output Controller 16.1 GPIO Instance in FE310-G000 FE310-G000 contains one GPIO instance. Its address and parameters are shown in Table 46. Table 46: GPIO Instance Instance Number Address ngpio 0x10012000 16.2 Memory Map The memory map for the GPIO control registers is shown in Table 47. The GPIO memory map has been designed to require only naturally-aligned 32-bit memory accesses.

  • Page 77: Input / Output Values

    When configured as inputs, each pin has an internal pull-up which can be enabled by software. At reset, all pins are set as inputs, and pull-ups are disabled. 16.6 Drive Strength When configured as output, each pin has a software-controllable drive strength. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 74...

  • Page 78: Output Inversion

    If there is no IOFx for a pin configured with IOFx, the pin reverts to full software control. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 75...

  • Page 79: Universal Asynchronous Receiver/Transmitter (Uart)

    The UART peripheral does not support hardware flow control or other modem control signals, or synchronous serial data transfers. 17.2 UART Instances in FE310-G000 FE310-G000 contains two UART instances. Their addresses and parameters are shown in Table 48. Table 48: UART Instances...

  • Page 80: Memory Map

    Table 50: Transmit Data Register Transmit Data Register ( txdata Register Offset Bits Field Name Attr. Rst. Description [7:0] Transmit data data [30:8] Reserved Transmit FIFO full full SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 77...

  • Page 81: Receive Data Register (Rxdata)

    Table 52: Transmit Control Register Transmit Control Register ( txctrl Register Offset Bits Field Name Attr. Rst. Description Transmit enable txen Number of stop bits nstop [15:2] Reserved [18:16] Transmit watermark level txcnt [31:19] Reserved SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 78...

  • Page 82: Receive Control Register (Rxctrl)

    Table 54: UART Interrupt Enable Register UART Interrupt Enable Register ( 0x10 Register Offset Bits Field Name Attr. Rst. Description Transmit watermark interrupt enable txwm Receive watermark interrupt enable rxwm SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 79...

  • Page 83: Baud Rate Divisor Register (Div)

    (MHz) Target Baud (Hz) Divisor Actual Baud (Hz) Error (%) tlclk 31250 31250 115200 117647 31250 31250 115200 115107 0.08 250000 250000 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 80...
  • Page 84 Table 57: Baud Rate Divisor Register Baud Rate Divisor Register ( 0x18 Register Offset Field Bits Attr. Rst. Description Name [15:0] Baud rate divisor. bits wide, and the reset div_width value is div_init [31:16] Reserved SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 81...

  • Page 85: Serial Peripheral Interface (Spi)

    Hardware interlocks ensure that the current transfer completes before mode transitions and control register updates take effect. 18.2 SPI Instances in FE310-G000 FE310-G000 contains three SPI instances. Their addresses and parameters are shown in Table Table 58: SPI Instances Instance...

  • Page 86: Memory Map

    0x18 csmode Reserved 0x1C Reserved 0x20 Reserved 0x24 Delay control 0 0x28 delay0 Delay control 1 0x2C delay1 Reserved 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Frame format 0x40 Reserved 0x44 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 83...

  • Page 87: Serial Clock Divisor Register (Sckdiv)

    Table 60: Serial Clock Divisor Register Serial Clock Divisor Register ( sckdiv Register Offset Bits Field Name Attr. Rst. Description [11:0] Divisor for serial clock. bits wide. div_width [31:12] Reserved SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 84...

  • Page 88: Serial Clock Mode Register (Sckmode)

    The reset value is Table 64: Chip Select ID Register Chip Select ID Register ( csid 0x10 Register Offset Bits Field Name Attr. Rst. Description SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 85...

  • Page 89: Chip Select Default Register (Csdef)

    • Direct-mapped flash mode is enabled. Table 66: Chip Select Mode Register Chip Select Mode Register ( csmode 0x18 Register Offset Bits Field Name Attr. Rst. Description [1:0] Chip select mode mode [31:2] Reserved SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 86...

  • Page 90: Delay Control Registers (Delay0 And Delay1)

    [7:0] CS to SCK Delay cssck [15:8] Reserved [23:16] SCK to CS Delay sckcs [31:24] Reserved Table 69: Delay Control Register 1 Delay Control Register 1 ( delay1 0x2C Register Offset SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 87...

  • Page 91: Frame Format Register (Fmt)

    0 otherwise. [15:4] Reserved [19:16] Number of bits per frame [31:20] Reserved Table 71: SPI Protocol. Unused DQ pins are tri-stated. Value Description Data Pins Single DQ0 (MOSI), DQ1 (MISO) SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 88...

  • Page 92: Transmit Data Register (Txdata)

    Table 74: Transmit Data Register Transmit Data Register ( txdata Register Offset 0x48 Bits Field Name Attr. Rst. Description [7:0] Transmit data data [30:8] Reserved FIFO full flag full SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 89...

  • Page 93: Receive Data Register (Rxdata)

    Transmit watermark. The reset value is 1 for flash-enabled txmark controllers, 0 otherwise. [31:3] Reserved 18.14 Receive Watermark Register ( rxmark register specifies the threshold at which the Rx FIFO watermark interrupt triggers. rxmark The reset value is SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 90...

  • Page 94: Spi Interrupt Registers (Ie And Ip)

    Reserved Table 79: SPI Watermark Interrupt Pending Register SPI Watermark Interrupt Pending Register ( 0x74 Register Offset Bits Field Name Attr. Rst. Description Transmit watermark pending txwm Receive watermark pending rxwm SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 91...

  • Page 95: Spi Flash Interface Control Register (Fctrl)

    Enable sending of command cmd_en [3:1] Number of address bytes (0 to 4) addr_len [7:4] Number of dummy cycles pad_cnt [9:8] Protocol for transmitting command cmd_proto [11:10] Protocol for transmitting address and padding addr_proto SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 92...
  • Page 96 Table 81: SPI Flash Instruction Format Register [13:12] Protocol for receiving data bytes data_proto [15:14] Reserved [23:16] Value of command byte cmd_code [31:24] First 8 bits to transmit during dummy cycles pad_code SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 93...

  • Page 97: Pulse Width Modulator (Pwm)

    ) up to 16 bits, with the example cmpwidth described here having the full 16 bits. To support clock scaling, the register is 15 bits pwmcount wider than the comparator precision cmpwidth SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 94...

  • Page 98: Pwm Instances In Fe310-G000

    Chapter 19 Pulse Width Modulator (PWM) Figure 10: PWM Peripheral 19.2 PWM Instances in FE310-G000 FE310-G000 contains three PWM instances. Their addresses and parameters are shown in Table 82. Table 82: PWM Instances Instance Number Address ncmp cmpwidth 0x10015000 0x10025000 0x10035000 19.3 PWM Memory Map...

  • Page 99: Pwm Count Register (Pwmcount)

    Chapter 19 Pulse Width Modulator (PWM) Table 83: SiFive PWM memory map, offsets relative to PWM peripheral base address Offset Name Description PWM configuration register 0x00 pwmcfg Reserved 0x04 PWM count register 0x08 pwmcount Reserved 0x0C Scaled PWM count register...

  • Page 100: Pwm Configuration Register (Pwmcfg)

    PWM2 Compare Center pwmcmp2center PWM3 Compare Center pwmcmp3center [23:20] Reserved PWM0/PWM1 Compare Gang pwmcmp0gang PWM1/PWM2 Compare Gang pwmcmp1gang PWM2/PWM3 Compare Gang pwmcmp2gang PWM3/PWM0 Compare Gang pwmcmp3gang PWM0 Interrupt Pending pwmcmp0ip SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 97...

  • Page 101: Scaled Pwm Count Register (Pwms)

    Table 86: Scaled PWM Count Register Scaled PWM Count Register ( pwms 0x10 Register Offset Bits Field Name Attr. Rst. Description [15:0] Scaled PWM count register. bits wide. pwms cmpwidth SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 98...

  • Page 102: Pwm Compare Registers (Pwmcmp0-Pwmcmp3)

    Register Offset Bits Field Name Attr. Rst. Description [15:0] PWM 2 Compare Value pwmcmp2 [31:16] Reserved Table 90: PWM 3 Compare Register PWM 3 Compare Register ( pwmcmp3 0x2C Register Offset SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 99...

  • Page 103: Deglitch And Sticky Circuitry

    SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 100...

  • Page 104: Generating Left- Or Right-Aligned Pwm Waveforms

    At a 16 MHz bus clock rate with 16-bit precision, this limits the fastest PWM cycle to 244 Hz, or 62.5 kHz with 8-bit precision. Higher bus clock rates allow proportion- SiFive FE310-G000 Manual: v3p2 © SiFive, Inc.
  • Page 105 When a comparator is operating in center mode, the deglitch circuit allows one 0-to-1 transition during the first half of the cycle and one 1-to-0 transition during the second half of the cycle. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc.

  • Page 106: Generating Arbitrary Pwm Waveforms Using Ganging

    The PWM peripheral can also be used as a regular timer with no counter reset ( =0), pwmzerocmp where the comparators are now used to provide timer interrupts. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 103...

  • Page 107: Debug

    Chapter 20 Debug This chapter describes the operation of SiFive debug hardware, which follows The RISC‑V Debug Specification 0.11. Currently only interactive debug and hardware breakpoints are sup- ported. 20.1 Debug CSRs This section describes the per-hart trace and debug registers (TDRs), which are mapped into...

  • Page 108: Trace And Debug Register Select (Tselect)

    Type of the trace & debug register selected tselect Table 95: CSRs tdata2/3 Trace and Debug Data Registers 2 and 3 tdata2/3 Bits Field Name Attr. Description [31:0] TDR-Specific Data SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 105...

  • Page 109: Debug Control And Status Register (Dcsr)

    Debug ROM. The debugger may use it as described in The RISC‑V Debug Specifi- cation 0.11. 20.2 Breakpoints The FE310-G000 supports two hardware breakpoint registers per hart, which can be flexibly shared between debug mode and machine mode. When a breakpoint register is selected with...

  • Page 110: Breakpoint Match Control Register Mcontrol

    Breakpoint action to take. 0 or 1. timing WARL Timing of the breakpoint. Always 0. select WARL Perform match on address or data. Always 0. Reserved WPRI Reserved [26:21] maskmax Largest supported NAPOT range SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 107...
  • Page 111 Table 99: NAPOT Size Encoding Match type and size maddress Exact 1 byte a…aaaaaa 2-byte NAPOT range a…aaaaa0 4-byte NAPOT range a…aaaa01 8-byte NAPOT range a…aaa011 16-byte NAPOT range a…aa0111 SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 108...

  • Page 112: Breakpoint Match Address Register (Maddress)

    0). Typically, a debugger will leave the breakpoints alone until it needs them, tdrtype either because a user explicitly requested one or because the user is debugging code in ROM. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 109...

  • Page 113: Debug Memory Map

    (offset from register and one free data register, which holds the hart ID. The set of valid component identifiers is defined by each implementation. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 110...

  • Page 114: Debug Ram (0X400-0X43F)

    20.3.2 Debug RAM ( – 0x400 0x43f SiFive systems provide at least the minimal required amount of Debug RAM, which is 28 bytes for an RV32 system and 64 bytes for an RV64 system. 20.3.3 Debug ROM ( – 0x800 0xFFF This ROM region holds the debug routines on SiFive systems.

  • Page 115: Debug Interface

    Chapter 21 Debug Interface The SiFive FE310-G000 includes the JTAG debug transport module (DTM) described in The RISC‑V Debug Specification 0.11. This enables a single external industry-standard 1149.1 JTAG interface to test and debug the system. The JTAG interface is directly connected to input pins.

  • Page 116: Resetting Jtag Logic

    The JTAG logic always operates in its own clock domain clocked by . The JTAG logic jtag_TCK is fully static and has no minimum clock frequency. The maximum frequency is part- jtag_TCK specific. SiFive FE310-G000 Manual: v3p2 © SiFive, Inc. Page 113...

  • Page 117: Jtag Standard Instructions

    The JTAG DTM implements the BYPASS and IDCODE instructions. On the FE310-G000, the IDCODE is set to 0x10E31913 21.5 JTAG Debug Commands The JTAG DEBUG instruction gives access to the SiFive debug module by connecting the debug scan register between jtag_TDI jtag_TDO...

  • Page 118: References

    Chapter 22 References Visit the SiFive forums for support and answers to frequently asked questions: https://forums.sifive.com [1] A. Waterman and K. Asanovic, Eds., The RISC-V Instruction Set Manual, Volume I: User- Level ISA, Version 2.2, May 2017. [Online]. Available: https://riscv.org/specifications/ [2] ——, The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10,...

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