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Table of Contents
Related Manuals for SiFive E31
Summary of Contents for SiFive E31
- Page 1 SiFive E31 Core Complex Manual v2p0 © SiFive, Inc.
- Page 2 SiFive does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, spe- cial, exemplary, or consequential damages.
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Page 3: Table Of Contents
Contents Introduction ......................4 ..................4 E31 Core Complex Overview ....................... 5 E31 RISC‑V Core ......................5 Debug Support ........................6 Interrupts ......................6 Memory System List of Abbreviations and Terms ..............7 E31 RISC-V Core ....................8 ..................8 Instruction Memory System .................. - Page 4 ..............17 5.3.1 Machine Status Register (mstatus) ............17 5.3.2 Machine Interrupt Enable Register (mie) ...............18 5.3.3 Machine Interrupt Pending (mip) ..............18 5.3.4 Machine Cause Register (mcause) ................20 5.3.5 Machine Trap Vector (mtvec) ..................... 21 Interrupt Priorities ....................... 21 Interrupt Latency Core Local Interruptor (CLINT) ..............22 ....................
- Page 5 ..................34 8.2.3 Breakpoint Execution ........35 8.2.4 Sharing Breakpoints Between Debug and Machine Mode ....................35 Debug Memory Map ..........35 8.3.1 Debug RAM and Program Buffer (0x300–0x3FF) ................35 8.3.2 Debug ROM (0x800–0xFFF) ............36 8.3.3 Debug Flags (0x100–0x110, 0x400–0x7FF) ................... 36 8.3.4 Safe Zero Address References...
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Page 6: Introduction
Table 1: E31 Core Complex Feature Set 1.1 E31 Core Complex Overview An overview of the SiFive E31 Core Complex is shown in Figure 1. This RISC-V Core IP includes a 32-bit RISC‑V microcontroller core, memory interfaces including an instruction cache... -
Page 7: E31 Risc-V Core
Copyright © 2017–2018, SiFive Inc. All rights reserved. Figure 1: E31 Core Complex Block Diagram The E31 Core Complex memory map is detailed in Chapter 4, and the interfaces are described in full in the E31 Core Complex User Guide. -
Page 8: Interrupts
Chapter 7. 1.5 Memory System The E31 Core Complex memory system has Tightly Integrated Instruction and Data Memory sub-systems optimized for high performance. The instruction subsystem consists of a 16 KiB 2-way instruction cache with the ability to reconfigure a single way into a fixed-address tightly integrated memory. -
Page 9: List Of Abbreviations And Terms
JTAG Joint Test Action Group Loosely Integrated Memory. Used to describe memory space delivered in a SiFive Core Complex but not tightly integrated to a CPU core. Physical Memory Protection PLIC Platform-Level Interrupt Controller. The global interrupt controller in a RISC-V system. -
Page 10: E31 Risc-V Core
Instruction Tightly Integrated Memory (ITIM), which is further described in Section 3.1.1. See the E31 Core Complex Memory Map in Chapter 4 for a description of exe- cutable address regions that are denoted by the attribute X. -
Page 11: I-Cache Reconfigurability
The E31 implements the standard Compressed (C) extension to the RISC‑V architecture, which allows for 16-bit RISC‑V instructions. 3.3 Execution Pipeline The E31 execution unit is a single-issue, in-order pipeline. The pipeline comprises five stages: instruction fetch, instruction decode and register fetch, execute, data memory access, and regis- ter writeback. -
Page 12: Data Memory System
See The RISC‑V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1 for more infor- mation on the instructions added by this extension. 3.6 Local Interrupts The E31 supports up to 16 local interrupt sources that are routed directly to the core. See Chap- ter 5 for a detailed description of Local Interrupts. -
Page 13: Supported Modes
3.8.1 Functional Description The E31 includes a PMP unit, which can be used to restrict access to memory and isolate processes from each other. The E31 PMP unit has 8 regions and a minimum granularity of 4 bytes. Overlapping regions are permitted. -
Page 14: Hardware Performance Monitor
3.9 Hardware Performance Monitor The E31 Core Complex supports a basic hardware performance monitoring facility compliant with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. The CSR holds a count of the number of clock cycles the hart has executed since some mcycle arbitrary time in the past. - Page 15 Copyright © 2017–2018, SiFive Inc. All rights reserved. Machine Hardware Performance Monitor Event Register Instruction Commit Events, [7:0] = 0 mhpeventX Bits Meaning Exception taken Integer load instruction retired Integer store instruction retired Atomic memory operation retired System instruction retired...
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Page 16: Memory Map
0x8000_FFFF RWX A Memory (DTIM) On Core Complex (64 KiB) Address Space Reserved 0x8001_0000 0xFFFF_FFFF Table 4: E31 Core Complex Memory Map. Memory Attributes: R - Read, W - Write, X - Exe- cute, C - Cacheable, A - Atomics... -
Page 17: Interrupts
Chapter 5 Interrupts This chapter describes how interrupt concepts in the RISC‑V architecture apply to the E31 Core Complex. The definitive resource for information about the RISC‑V interrupt architecture is The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. -
Page 18: Interrupt Entry And Exit
Copyright © 2017–2018, SiFive Inc. All rights reserved. Figure 2: E31 Core Complex Interrupt Architecture Block Diagram. 5.2 Interrupt Entry and Exit When a RISC‑V hart takes an interrupt, the following occurs: • The value of is copied into , and then is cleared, mstatus.MIE... -
Page 19: Interrupt Control Status Registers
A summary of the fields related to interrupts in mstatus the E31 Core Complex is provided in Table 5. Note that this is not a complete description of as it contains fields unrelated to interrupts. For the full description of , please... -
Page 20: Machine Interrupt Pending (Mip)
Copyright © 2017–2018, SiFive Inc. All rights reserved. Machine Interrupt Enable Register Bits Field Name Attr. Description [2:0] Reserved WPRI MSIE Machine Software Interrupt Enable [6:4] Reserved WPRI MTIE Machine Timer Interrupt Enable [10:8] Reserved WPRI MEIE Machine External Interrupt Enable... - Page 21 Copyright © 2017–2018, SiFive Inc. All rights reserved. encoding as the bit positions in . For example, a Machine Timer Interrupt causes mcause be set to is also used to indicate the cause of synchronous exceptions, in 0x8000_0007 mcause which case the most-significant bit of is set to 0.
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Page 22: Machine Trap Vector (Mtvec)
+ 0x2C for any global mtvec.BASE interrupt. See Table 10 for a description of the register. See Table 11 for a description of the mtvec field. See Table 9 for the E31 Core Complex interrupt exception code values. mtvec.MODE... -
Page 23: Interrupt Priorities
• Machine timer interrupts 5.5 Interrupt Latency Interrupt latency for the E31 Core Complex is 4 cycles, as counted by the numbers of cycles it takes from signaling of the interrupt to the hart to the first instruction fetch of the handler. -
Page 24: Core Local Interruptor (Clint)
Core Local Interruptor (CLINT) The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. The E31 Core Complex CLINT complies with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 6.1 CLINT Memory Map Table 12 shows the memory map for CLINT on SiFive E31 Core Complex. -
Page 25: Timer Registers
6.3 Timer Registers is a 64-bit read-write register that contains the number of cycles counted from the mtime signal described in the E31 Core Complex User Guide. A timer interrupt is pending rtc_toggle whenever is greater than or equal to the value in the register. -
Page 26: Platform-Level Interrupt Controller (Plic)
7.1 Memory Map The memory map for the E31 Core Complex PLIC control registers is shown in Table 13. The PLIC memory map has been designed to only require naturally aligned 32-bit memory accesses. -
Page 27: Interrupt Sources
Table 13: SiFive PLIC Register Map. Only naturally aligned 32-bit memory accesses are required. 7.2 Interrupt Sources The E31 Core Complex has 127 interrupt sources. These are exposed at the top level via the signals. Any unused inputs should be tied to logic 0. -
Page 28: Interrupt Priorities
7.3 Interrupt Priorities Each PLIC interrupt source can be assigned a priority by writing to its 32-bit memory-mapped register. The E31 Core Complex supports 7 levels of priority. A priority value of 0 is priority reserved to mean "never interrupt" and effectively disables the interrupt. Priority 1 is the lowest active priority, and priority 7 is the highest. -
Page 29: Interrupt Enables
Copyright © 2017–2018, SiFive Inc. All rights reserved. PLIC Interrupt Pending Register 4 ( pending4 Base Address 0x0C00_100C Bits Field Name Attr. Rst. Description Interrupt 96 Pend- Pending bit for global interrupt 96 … Interrupt 127 Pending bit for global interrupt 127... -
Page 30: Priority Thresholds
A successful claim also atomically clears the corresponding pending bit on the interrupt source. A E31 Core Complex hart can perform a claim at any time, even if the MEIP bit in its (Table 7) register is not set. - Page 31 Copyright © 2017–2018, SiFive Inc. All rights reserved. PLIC Claim/Complete Register ( claim Base Address 0x0C20_0004 [31:0] Interrupt Claim/ A read of zero indicates that no inter- Complete for Hart rupts are pending. A non-zero read 0 M-Mode contains the id of the highest pending interrupt.
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Page 32: Debug
Chapter 8 Debug This chapter describes the operation of SiFive debug hardware, which follows The RISC‑V Debug Specification 0.13. Currently only interactive debug and hardware breakpoints are sup- ported. 8.1 Debug CSRs This section describes the per-hart trace and debug registers (TDRs), which are mapped into... -
Page 33: Trace And Debug Data Registers (Tdata1-3)
Copyright © 2017–2018, SiFive Inc. All rights reserved. Trace and Debug Select Register tselect Bits Field Name Attr. Description [31:0] index WARL Selection index of trace and debug registers Table 22: tselect field is a WARL field that does not hold indices of unimplemented TDRs. Even if index can hold a TDR index, it does not guarantee the TDR exists. -
Page 34: Debug Control And Status Register (Dcsr)
Debug ROM. The debugger may use it as described in The RISC‑V Debug Specifi- cation 0.13. 8.2 Breakpoints The E31 Core Complex supports four hardware breakpoint registers per hart, which can be flex- ibly shared between debug mode and machine mode. When a breakpoint register is selected with... - Page 35 Copyright © 2017–2018, SiFive Inc. All rights reserved. Breakpoint Control Register ( mcontrol Register Offset Bits Field Attr. Rst. Description Name WARL Address match on LOAD WARL Address match on STORE WARL Address match on Instruction FETCH WARL Address match on User Mode...
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Page 36: Breakpoint Match Address Register (Maddress)
Copyright © 2017–2018, SiFive Inc. All rights reserved. breakpoint register giving the address 1 byte above the breakpoint range, and using the chain bit to indicate both must match for the action to be taken. NAPOT ranges make use of low-order bits of the associated breakpoint address register to... -
Page 37: Sharing Breakpoints Between Debug And Machine Mode
– 0x300 0x3FF The E31 Core Complex has 16 32-bit words of program buffer for the debugger to direct a hart to execute arbitrary RISC-V code. Its location in memory can be determined by executing aiupc instructions and storing the result into the program buffer. -
Page 38: Debug Flags (0X100-0X110, 0X400-0X7Ff)
The specific behavior of the flags is not further documented here. 8.3.4 Safe Zero Address In the E31 Core Complex, the debug module contains the address in the memory map. Reads to this address always return 0, and writes to this address have no impact. This property allows a "safe"... -
Page 39: References
Chapter 9 References Visit the SiFive forums for support and answers to frequently asked questions: https://forums.sifive.com [1] A. Waterman and K. Asanovic, Eds., The RISC-V Instruction Set Manual, Volume I: User- Level ISA, Version 2.2, May 2017. [Online]. Available: https://riscv.org/specifications/ [2] ——, The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10,...
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