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SiFive E3* Core IP Series User Manual

Fpga eval kit
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SiFive Core IP FPGA Eval Kit User Guide
v3p0
© SiFive, Inc.

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  • Page 1 SiFive Core IP FPGA Eval Kit User Guide v3p0 © SiFive, Inc.
  • Page 2 SiFive Core IP FPGA Eval Kit User Guide v3p0...

  • Page 3: Sifive Core Ip Fpga Eval Kit User Guide

    fitness for a particular purpose and non-infringement. SiFive does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, special, exemplary, or consequential damages.
  • Page 4 SiFive Core IP FPGA Eval Kit User Guide v3p0...

  • Page 5: Table Of Contents

    Contents SiFive Core IP FPGA Eval Kit User Guide List of Figures Introduction About this Document ........
  • Page 6 SiFive Core IP FPGA Eval Kit User Guide v3p0 Default Demo Program ....... . . 13 5.2.1...

  • Page 7: List Of Figures

    List of Figures 3.1 Debugging Connections between Olimex ARM-USB-TINY-H and Arty Board’s PMOD header JD ........3.2 Debug Connections To the Olimex ARM-USB-TINY-H .
  • Page 8 SiFive Core IP FPGA Eval Kit User Guide v3p0...

  • Page 9: Introduction

    Chapter 1 Introduction 1.1 About this Document This document gives necessary information for a user of the SiFive Core IP FPGA Eval Kit. To learn more about the functionality of your specific Core IP please read the appropriate Core IP Manual.
  • Page 10 SiFive Core IP FPGA Eval Kit User Guide v3p0...

  • Page 11: Required Hardware

    Chapter 2 Required Hardware The Core IP FPGA Eval Kit requires the following hardware: 2.1 Xilinx Arty A7 Artix-7 FPGA Evaluation Kit The Arty A7 is a Xilinx FPGA development board for makers and hobbyists. The Arty A7 comes in two FPGA variants: The Arty A7-35T features Xilinx XC7A35TICSG324-1L. The Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.

  • Page 12: Male-To-Female Jumper Cables (10)

    SiFive Core IP FPGA Eval Kit User Guide v3p0 2.5 Male-To-Female Jumper Cables (10) The connection between the Olimex ARM-USB-TINY-H and Core IP FPGA Eval Kit requires 10 connections. These can be made with Male-to-Female jumper cables. These cables are available from Adafruit in convenient rip-apart ribbon cables: https://www.adafruit.com/products/826...

  • Page 13: Board Setup

    Chapter 3 Board Setup 3.1 Connecting the USB Interface Connect the USB Type A to Micro-B cable between the USB-JTAG port (J10) of the Arty and the host machine. This provides UART console access to the Core IP FPGA Eval Kit as well as a 5V power source for the board.

  • Page 14: Debugging Connections Between Olimex Arm-Usb-Tiny-H And Arty Board's Pmod Header Jd

    SiFive Core IP FPGA Eval Kit User Guide v3p0 Signal ARM-USB- Suggested Freedom E310 Arty Name TINY-H Pin Jumper Dev Kit JD Pin Number Number Color VREF VREF brown 6 (“VCC”) nTRST orange yellow green blue purple black 5 (“GND”)

  • Page 15: Photo Of The Arty Board Showing Usb And Debug Connections

    Copyright © 2016-2019, SiFive Inc. All rights reserved. Figure 3.4: Photo of the Arty Board showing USB and Debug Connections...
  • Page 16 SiFive Core IP FPGA Eval Kit User Guide v3p0...

  • Page 17: Fpga Flash Programming File

    Chapter 4 FPGA Flash Programming File The Xilinx Artix-7 35T or 100T FPGA configures on power-on from an on-board 16MB QuadSPI Flash. To program the Arty Board, locate the desired MCS file within your Core IP package. For example, sifive_coreip_[XX]_FPGA_Evaluation_Arty_[35|100]T_v[XXX]_rc[xx].mcs The Xilinx Vivado Design Suite is used for flash programming.

  • Page 18: Programming The Arty 100T Spi Flash

    SiFive Core IP FPGA Eval Kit User Guide v3p0 8. Select OK 9. Once the programming completes in Vivado, press the “PROG” Button on the Arty Board to load the image into the FPGA. 4.2 Programming the Arty 100T SPI Flash To program the Arty 100T SPI Flash with Vivado take the following steps: 1.

  • Page 19: Boot And Run

    Chapter 5 Boot and Run 5.1 Serial Setup Using a terminal emulator such as GNU screen on Linux or a terminal on Windows, open a console connection from the host computer to the Core IP FPGA Eval Kit. Set the following parameters: Speed 115200 Parity...
  • Page 20 SiFive Core IP FPGA Eval Kit User Guide v3p0 > sudo vi /etc/udev/rules.d/99-openocd.rules Add the following lines and save the file (if they are not already there): # These are for the HiFive1 Board SUBSYSTEM=="usb", ATTR{idVendor}=="0403", ATTR{idProduct}=="6011", MODE="664", GROUP="plugdev" SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="664", GROUP="plugdev"...

  • Page 21: Reset And Boot

    Copyright © 2016-2019, SiFive Inc. All rights reserved. 5.1.1 Reset and boot The FPGA Core IP Eval Kit’s boot code contains a jump to the external SPI Flash as described in the DTS file. For example,an E2/E3 or S5 Core IP FPGA Eval Kit’s reset vector is set using Switch 0 on the board.
  • Page 22 SiFive Core IP FPGA Eval Kit User Guide v3p0 55555 BUILD TIME : Feb 28 2019 : 00:00:00 Welcome to the E21 Core IP FPGA Evaluation Kit!

  • Page 23: Software Development Flow

    This section describes how to setup the toolchain and configure the SDK. The section also walks through building an example program and executing it in the RTL testbench included in a SiFive Core IP deliverable. In addition, the section will walk through how to import custom BSPs and...

  • Page 24: Setting Up Freedom-E-Sdk

    • RISC-V GNU Toolchain • RISC-V OpenOCD (for use with development board and FPGA targets) Pre-built versions of these softwares can be found on the SiFive Website. https://www.sifive.com/boards The pre-built tools have been carefully packaged to support both RISCV 32bit & 64bit ISAs and work on Linux, macOS, and Windows hosts.

  • Page 25: Freedom E Sdk Arty Bsp

    Copyright © 2016-2019, SiFive Inc. All rights reserved. 6.4 Freedom E SDK Arty BSP The Freedom Metal Compatibility Library layer uses, the board support package files, to provide the hardware abstraction layer. These bsp files can be found under the bsp folder in Freedom-E- SDK and are encapsulated entirely within each target directory.

  • Page 26: Using The Freedom E Sdk

    SiFive Core IP FPGA Eval Kit User Guide v3p0 Prints ”Hello, World!” to stdout, if a serial device is present on the target. ***return-pass*** Returns status code 0 indicating program success. ***return-fail*** Returns status code 1 indicating program failure. ***example-itim**** Demonstrates how to statically link application code into the Instruction Tightly Integrated Memory (ITIM) if an ITIM is present on the target.

  • Page 27: Debugging A Target Program

    Copyright © 2016-2019, SiFive Inc. All rights reserved. 6.6.3 Debugging a Target Program make BSP=metal [PROGRAM=hello] [TARGET=coreip-s51-arty] debug 6.6.4 Cleaning a Target Program Build Directory make BSP=metal [PROGRAM=hello] [TARGET=coreip-s51-arty] clean 6.6.5 Create a Standalone Project You can export a program to a standalone project directory using the standalone target. The resulting project will be locked to a specific TARGET.
  • Page 28 SiFive Core IP FPGA Eval Kit User Guide v3p0...

  • Page 29: Core Ip Fpga Eval Kit Memory Map

    7.1 Core IP FPGA Eval Kit Memory Map The FPGA design on the Core IP FPGA Eval Kit has an evaluation version of the SiFive E2 Core IP, as well as peripheral devices which are not included with the Core IP deliverable. These devices allow you to perform basic I/O to prototype and benchmark some basic applications.

  • Page 30: E2 Core Ip Fpga Eval Kit Block Diagram

    SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 7.1: E2 Core IP FPGA Eval Kit Block Diagram...
  • Page 31 Copyright © 2016-2019, SiFive Inc. All rights reserved. Table 7.1: Core IP FPGA Eval Kit GPIO Offset to Board Pin Number Peripheral Peripheral Offset Connections Global Interrupt Number UART UART TX/RX To USB Serial SWITCH 0 Direct Global SWITCH 1...
  • Page 32 SiFive Core IP FPGA Eval Kit User Guide v3p0 Table 7.2: Core IP FPGA Eval Kit Local Interrupts Mapping Local Interrupt Number (Index Hardware Input mip, mie, registers) Switch 0 Switch 1 Switch 2 Switch 3 Button 0 Button 1...

  • Page 33: E3 / S5 Core Ip Fpga Eval Kit Mcs Image Contents

    8.1 Core IP FPGA Eval Kit Memory Map The FPGA design on the Core IP FPGA Eval Kit has an evaluation version of the SiFive E3 / S5 Core IP, as well as peripheral devices which are not included with the Core IP deliverable. These devices allow you to perform basic I/O to prototype and benchmark some basic applications.

  • Page 34: E3 / S5 Core Ip Fpga Eval Kit Block Diagram

    SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 8.1: E3 / S5 Core IP FPGA Eval Kit Block Diagram...
  • Page 35 Copyright © 2016-2019, SiFive Inc. All rights reserved. Table 8.1: Core IP FPGA Eval Kit GPIO Offset to Board Pin Number Peripheral Peripheral Offset Connections Global Interrupt Number UART UART TX/RX To USB Serial SWITCH 0 Direct Global SWITCH 1...
  • Page 36 SiFive Core IP FPGA Eval Kit User Guide v3p0 Table 8.2: Core IP FPGA Eval Kit Local Interrupts Mapping Local Interrupt Number (Index Hardware Input mip, mie, registers) Switch 0 Switch 1 Switch 2 Switch 3 Button 0 Button 1...

  • Page 37: E7 / S7 Mcs Image Contents

    9.1 Core IP FPGA Eval Kit Memory Map The FPGA design on the Core IP FPGA Eval Kit has an evaluation version of the SiFive E7 / S7 Core IP, as well as peripheral devices which are not included with the Core IP deliverable. These devices allow you to perform basic I/O to prototype and benchmark some basic applications.

  • Page 38: E7 / S7 Core Ip Fpga Eval Kit Block Diagram

    SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 9.1: E7 / S7 Core IP FPGA Eval Kit Block Diagram...
  • Page 39 Copyright © 2016-2019, SiFive Inc. All rights reserved. Table 9.1: Core IP FPGA Eval Kit GPIO Offset to Board Pin Number Peripheral Peripheral Offset Connections Global Interrupt Number UART UART TX/RX To USB Serial SWITCH 0 Direct Global SWITCH 1...
  • Page 40 SiFive Core IP FPGA Eval Kit User Guide v3p0 Table 9.2: Core IP FPGA Eval Kit Local Interrupts Mapping Local Interrupt Number (Index Hardware Input mip, mie, registers) Switch 0 Switch 1 Switch 2 Switch 3 Button 0 Button 1...

  • Page 41: For More Information

    Chapter 10 For More Information Additional information, the latest version of this guide, and supporting files can be found at https://www.sifive.com More information about RISC-V in general is available at http://riscv.org SiFive thoughts, ideas, and news at https://www.sifive.com/blog/ Webinars at https://info.sifive.com/risc-v-webinar...

This manual is also suitable for:

E2* core ip seriesE7* core ip seriesS7* core ip seriesS5* core ip series

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