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SiFive FE310-G002 Manual

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SiFive FE310-G002 Manual
v19p05
© SiFive, Inc.

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Summary of Contents for SiFive FE310-G002

  • Page 1 SiFive FE310-G002 Manual v19p05 © SiFive, Inc.
  • Page 2 SiFive does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, spe- cial, exemplary, or consequential damages.

  • Page 3: Table Of Contents

    Contents Introduction ......................8 ....................8 FE310-G002 Overview ..................... 10 E31 RISC‑V Core ......................... 10 Interrupts ................... 11 On-Chip Memory System .................... 11 Always-On (AON) Block ......................11 GPIO Complex .............11 Universal Asynchronous Receiver/Transmitter ..............11 Hardware Serial Peripheral Interface (SPI) .....................
  • Page 4 Boot Process ......................23 ......................23 Reset Vector ..................24 5.1.1 Mask ROM (MROM) ............24 5.1.2 One-Time Programmable (OTP) Memory ..............24 5.1.3 Quad SPI Flash Controller (QSPI) Clock Generation ....................25 ..................25 Clock Generation Overview ..................26 PRCI Address Space Usage ........26 Internal Trimmable Programmable 72 MHz Oscillator (HFROSC) .............27...
  • Page 5 ....................... 41 Interrupt Latency Core-Local Interruptor (CLINT) ..............42 ....................42 CLINT Memory Map ......................42 MSIP Registers ......................43 Timer Registers Platform-Level Interrupt Controller (PLIC) ...........44 ......................44 10.1 Memory Map ....................45 10.2 Interrupt Sources ....................46 10.3 Interrupt Priorities ....................
  • Page 6 PMU Interrupt Enables (pmuie) and Wakeup Cause (pmucause) Real-Time Clock (RTC) ................... 71 ...........71 16.1 RTC Count Registers (rtccounthi/rtccountlo) ..............72 16.2 RTC Configuration Register (rtccfg) ................72 16.3 RTC Compare Register (rtccmp) General Purpose Input/Output Controller (GPIO) ......74 ................. 76 17.1 GPIO Instance in FE310-G002...
  • Page 7 17.8 HW I/O Functions (IOF) Universal Asynchronous Receiver/Transmitter (UART) ....79 ...................... 79 18.1 UART Overview ................79 18.2 UART Instances in FE310-G002 ......................80 18.3 Memory Map ................80 18.4 Transmit Data Register (txdata) ................80 18.5 Receive Data Register (rxdata) .................81...
  • Page 8 19.17 SPI Flash Instruction Format Register (ffmt) Pulse Width Modulator (PWM) ..............94 ....................... 94 20.1 PWM Overview ................95 20.2 PWM Instances in FE310-G002 ....................95 20.3 PWM Memory Map ................96 20.4 PWM Count Register (pwmcount) ..............97 20.5 PWM Configuration Register (pwmcfg) .................98...
  • Page 9 ..................108 22.2.3 Breakpoint Execution ........109 22.2.4 Sharing Breakpoints Between Debug and Machine Mode ....................109 22.3 Debug Memory Map ...........109 22.3.1 Debug RAM and Program Buffer (0x300–0x3FF) ................109 22.3.2 Debug ROM (0x800–0xFFF) ..........110 22.3.3 Debug Flags (0x100–0x110, 0x400–0x7FF) ..................110 22.3.4 Safe Zero Address Debug Interface...

  • Page 10: Introduction

    The FE310-G002 is the second revision of the General Purpose Freedom E300 family. The FE310-G002 is built around the E31 Core Complex instantiated in the Freedom E300 plat- form and fabricated in the TSMC CL018G 180nm process. This manual serves as an architec- tural reference and integration guide for the FE310-G002.
  • Page 11 Copyright © 2019, SiFive Inc. All rights reserved. Figure 1: FE310-G002 top-level block diagram.

  • Page 12: E31 Risc-V Core

    1.3 Interrupts The FE310-G002 includes a RISC-V standard platform-level interrupt controller (PLIC), which supports 52 global interrupts with 7 priority levels. The FE310-G002 also provides the standard RISC‑V machine-mode timer and software interrupts via the Core-Local Interruptor (CLINT). Interrupts are described in Chapter 8. The CLINT is described in Chapter 9. The PLIC is...

  • Page 13: On-Chip Memory System

    1.8 Hardware Serial Peripheral Interface (SPI) There are 3 serial peripheral interface (SPI) controllers. Each controller provides a means for serial communication between the FE310-G002 and off-chip devices, like quad-SPI Flash mem- ory. Each controller supports master-only operation over single-lane, dual-lane, and quad-lane protocols.

  • Page 14: Pulse Width Modulation

    GPIO output pins and can also be used to generate several forms of internal timer interrupt. The PWM peripherals are described in Chapter 20. 1.10 I²C The FE310-G002 has an I²C controller to communicate with external I²C devices, such as sen- sors, ADCs, etc. The I²C is described in detail in Chapter 21.

  • Page 15: List Of Abbreviations And Terms

    Chapter 2 List of Abbreviations and Terms...
  • Page 16 JTAG Joint Test Action Group Loosely Integrated Memory. Used to describe memory space delivered in a SiFive Core Complex but not tightly integrated to a CPU core. Physical Memory Protection PLIC Platform-Level Interrupt Controller. The global interrupt controller in a RISC-V system.

  • Page 17: E31 Risc-V Core

    The core caches instructions from executable addresses, with the exception of the Instruction Tightly Integrated Memory (ITIM), which is further described in Section 3.1.1. See the FE310-G002 Memory Map in Chapter 4 for a description of executable address regions that are denoted by the attribute X.

  • Page 18: I-Cache Reconfigurability

    Copyright © 2019, SiFive Inc. All rights reserved. 3.1.1 I-Cache Reconfigurability The instruction cache can be partially reconfigured into ITIM, which occupies a fixed address range in the memory map. ITIM provides high-performance, predictable instruction delivery. Fetching an instruction from ITIM is as fast as an instruction-cache hit, with no possibility of a cache miss.

  • Page 19: Data Memory System

    Copyright © 2019, SiFive Inc. All rights reserved. • MUL, MULH, MULHU, and MULHSU have a 5-cycle result latency. • DIV, DIVU, REM, and REMU have between a 2-cycle and 33-cycle result latency, depending on the operand values. The pipeline only interlocks on read-after-write and write-after-write hazards, so instructions may be scheduled to avoid stalls.

  • Page 20: Supported Modes

    Copyright © 2019, SiFive Inc. All rights reserved. 3.6 Supported Modes The E31 supports RISC‑V user mode, providing two levels of privilege: machine (M) and user (U). U-mode provides a mechanism to isolate application processes from each other and from trusted code running in M-mode.

  • Page 21: Hardware Performance Monitor

    Copyright © 2019, SiFive Inc. All rights reserved. 3.8 Hardware Performance Monitor The FE310-G002 supports a basic hardware performance monitoring facility compliant with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. The mcycle CSR holds a count of the number of clock cycles the hart has executed since some arbitrary time in the past.
  • Page 22 Copyright © 2019, SiFive Inc. All rights reserved. Machine Hardware Performance Monitor Event Register Instruction Commit Events, [7:0] = 0 mhpeventX Bits Meaning Exception taken Integer load instruction retired Integer store instruction retired Atomic memory operation retired System instruction retired...

  • Page 23: Memory Map

    Chapter 4 Memory Map The memory map of the FE310-G002 is shown in Table 4.
  • Page 24 (512 MiB) Reserved 0x4000_0000 0x7FFF_FFFF E31 DTIM (16 KiB) 0x8000_0000 0x8000_3FFF RWX A On-Chip Volatile Memory Reserved 0x8000_4000 0xFFFF_FFFF Table 4: FE310-G002 Memory Map. Memory Attributes: R - Read, W - Write, X - Execute, C - Cacheable, A - Atomics...

  • Page 25: Boot Process

    Chapter 5 Boot Process The FE310-G002 supports booting from several sources, which are controlled using the Mode Select ( ) pins on the chip. All possible values are enumerated in Table 5. MSEL[1:0] MSEL Purpose loops forever waiting for debugger...

  • Page 26: Mask Rom (Mrom)

    Table 7: Target of the reset vector 5.1.1 Mask ROM (MROM) MROM is fixed at design time, and is located on the peripheral bus on FE310-G002, but instruc- tions fetched from MROM are cached by the core’s I-cache. The MROM contains an instruction at address...

  • Page 27: Clock Generation

    AON block (Chapter 13) or the PRCI block (Section 6.2). 6.1 Clock Generation Overview Figure 2: FE310-G002 clock generation scheme Figure 2 shows an overview of the FE310-G002 clock generation scheme. Most digital clocks on the chip are divided down from a central high-frequency clock produced from either hfclk the PLL or an on-chip trimmable oscillator.

  • Page 28: Prci Address Space Usage

    The PRCI registers are generally only made visible to machine-mode software. The AON block contains registers with similar functions, but only for the AON block units. Table 8 shows the memory map for the PRCI on the FE310-G002. Offset Name...

  • Page 29: External 16 Mhz Crystal Oscillator (Hfxosc)

    Copyright © 2019, SiFive Inc. All rights reserved. hfrosccfg: Ring Oscillator Configuration and Status ( hfrosccfg Register Offset Bits Field Name Attr. Rst. Description [5:0] Ring Oscillator Divider Register hfroscdiv [15:6] Reserved [20:16] Ring Oscillator Trim Register hfrosctrim 0x10 [29:21]...

  • Page 30: Internal High-Frequency Pll (Hfpll)

    Copyright © 2019, SiFive Inc. All rights reserved. When used to drive the PLL, the 16 MHz crystal oscillator output frequency must be divided by two in the first-stage divider of the PLL (i.e., ) to provide an 8 MHz reference clock to the VCO.
  • Page 31 Figure 3: Controlling the FE310-G002 PLL output frequency. field encodes the reference clock divide ratio as a 2-bit binary value, where the pllr[1:0] value is one less than the divide ratio (i.e., =4).

  • Page 32: Pll Output Divider

    Copyright © 2019, SiFive Inc. All rights reserved. (MHz) Legal multiplier frequency (MHz) refr pllf Table 12: Valid PLL multiply ratios. The multiplier setting in the table is given as the actual multiply ratio; the binary value stored in field should be...

  • Page 33: Internal Programmable Low-Frequency Ring Oscillator (Lfrosc)

    Copyright © 2019, SiFive Inc. All rights reserved. plloutdiv: PLL Final Divide Configuration ( plloutdiv Register Offset Bits Field Name Attr. Rst. Description [5:0] PLL Final Divider Value plloutdiv [7:6] Reserved [13:8] PLL Final Divide By 1 plloutdivby1 [31:14] Reserved...

  • Page 34: Alternate Low-Frequency Clock (Lfaltclk)

    Table 15: lfclkmux: Low-Frequency Clock Mux Control and Status 6.9 Clock Summary Table 16 summarizes the major clocks on the FE310-G002 and their initial reset conditions. At external reset, the AON domain is clocked by either the LFROSC or...

  • Page 35: Power Modes

    Chapter 7 Power Modes This chapter describes the different power modes available on the FE310-G002. The FE310-G002 supports three power modes: Run, Wait, and Sleep. 7.1 Run Mode Run mode corresponds to regular execution where the processor is running. Power consump- tion can be adjusted by varying the clock frequency of the processor and peripheral bus, and by enabling or disabling individual peripheral blocks.
  • Page 36 HFROSC at the default setting, and must reconfigure clocks to run from an alternate clock source (HFXOSC or PLL) or at a different setting on the HFROSC. Because the FE310-G002 has no internal power regulator, the PMU’s control of the power sup- plies is through chip outputs, .

  • Page 37: Interrupts

    Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 8.1 Interrupt Concepts The FE310-G002 supports Machine Mode interrupts. It also has support for the following types of RISC‑V interrupts: local and global. Local interrupts are signaled directly to an individual hart with a dedicated interrupt value. This...

  • Page 38: Interrupt Operation

    Copyright © 2019, SiFive Inc. All rights reserved. Figure 4: FE310-G002 Interrupt Architecture Block Diagram. 8.2 Interrupt Operation If the global interrupt-enable is clear, then no interrupts will be taken. If mstatus.MIE is set, then pending-enabled interrupts at a higher interrupt level will preempt cur- mstatus.MIE...

  • Page 39: Interrupt Control Status Registers

    A summary of the fields related to interrupts in mstatus the FE310-G002 is provided in Table 17. Note that this is not a complete description of mstatus as it contains fields unrelated to interrupts. For the full description of...
  • Page 40 See Table 18 for a description of the register. See Table 19 for a description of the mtvec field. See Table 23 for the FE310-G002 interrupt exception code values. mtvec.MODE Mode Direct When operating in direct mode all synchronous exceptions and asynchronous interrupts trap to address.

  • Page 41: Machine Interrupt Enable (Mie)

    Copyright © 2019, SiFive Inc. All rights reserved. 8.3.3 Machine Interrupt Enable ( Individual interrupts are enabled by setting the appropriate bit in the register. The regis- ter is described in Table 20. Machine Interrupt Enable Register Bits Field Name Attr.

  • Page 42: Interrupt Priorities

    8.4 Interrupt Priorities Individual priorities of global interrupts are determined by the PLIC, as discussed in Chapter 10. FE310-G002 interrupts are prioritized as follows, in decreasing order of priority: • Machine external interrupts • Machine software interrupts • Machine timer interrupts...

  • Page 43: Interrupt Latency

    Copyright © 2019, SiFive Inc. All rights reserved. 8.5 Interrupt Latency Interrupt latency for the FE310-G002 is 4 cycles, as counted by the numbers of cycles it takes from signaling of the interrupt to the hart to the first instruction fetch of the handler.

  • Page 44: Core-Local Interruptor (Clint)

    Chapter 9 Core-Local Interruptor (CLINT) The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. The FE310-G002 CLINT complies with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 9.1 CLINT Memory Map Table 24 shows the memory map for CLINT on SiFive FE310-G002.

  • Page 45: Timer Registers

    Copyright © 2019, SiFive Inc. All rights reserved. 9.3 Timer Registers is a 64-bit read-write register that contains the number of cycles counted from the mtime rtcclk input described in Chapter 13. A timer interrupt is pending whenever is greater than or...

  • Page 46: Platform-Level Interrupt Controller (Plic)

    Architecture, Version 1.10 and supports 52 interrupt sources with 7 priority levels. 10.1 Memory Map The memory map for the FE310-G002 PLIC control registers is shown in Table 25. The PLIC memory map has been designed to only require naturally aligned 32-bit memory accesses.

  • Page 47: Interrupt Sources

    10.2 Interrupt Sources The FE310-G002 has 52 interrupt sources. These are driven by various on-chip devices as listed in Table 26. These signals are positive-level triggered. In the PLIC, as specified in The RISC‑V Instruction Set Manual, Volume II: Privileged Architec-...

  • Page 48: Interrupt Priorities

    10.3 Interrupt Priorities Each PLIC interrupt source can be assigned a priority by writing to its 32-bit memory-mapped register. The FE310-G002 supports 7 levels of priority. A priority value of 0 is priority reserved to mean "never interrupt" and effectively disables the interrupt. Priority 1 is the lowest active priority, and priority 7 is the highest.

  • Page 49: Interrupt Enables

    Copyright © 2019, SiFive Inc. All rights reserved. PLIC Interrupt Pending Register 1 ( pending1 Base Address 0x0C00_1000 Bits Field Name Attr. Rst. Description Interrupt 0 Pend- Non-existent global interrupt 0 is hard- wired to zero Interrupt 1 Pend- Pending bit for global interrupt 1...

  • Page 50: Priority Thresholds

    WARL field, where the FE310-G002 supports a maximum threshold of 7. threshold The FE310-G002 masks all PLIC interrupts of a priority less than or equal to . For threshold example, a value of zero permits all interrupts with non-zero priority, whereas a threshold value of 7 masks all interrupts.

  • Page 51: Interrupt Completion

    Copyright © 2019, SiFive Inc. All rights reserved. pending interrupt. A successful claim also atomically clears the corresponding pending bit on the interrupt source. A FE310-G002 hart can perform a claim at any time, even if the MEIP bit in its (Table 21) register is not set.
  • Page 52 Copyright © 2019, SiFive Inc. All rights reserved. PLIC Claim/Complete Register ( claim Base Address 0x0C20_0004 [31:0] Interrupt Claim/ A read of zero indicates that no inter- Complete for Hart rupts are pending. A non-zero read 0 M-Mode contains the id of the highest pending interrupt.

  • Page 53: Error Device

    Chapter 11 Error Device The error device is a TileLink slave that responds to all requests with a TileLink error. It has no registers. The entire memory range discards writes and returns zeros on read. Both operation acknowledgments carry an error indication. The error device serves a dual role.

  • Page 54: One-Time Programmable Memory (Otp) Peripheral

    Chapter 12 One-Time Programmable Memory (OTP) Peripheral This chapter describes the operation of the One-Time Programmable Memory (OTP) Controller. Device configuration and power-supply control is principally under software control. The con- troller is reset to a state that allows memory-mapped reads, under the assumption that the con- troller’s clock rate is between 1 MHz and 37 MHz.
  • Page 55 Copyright © 2019, SiFive Inc. All rights reserved. Offset Name Description Programmed-I/O lock register 0x00 otp_lock OTP device clock signals 0x04 otp_ck OTP device output-enable signal 0x08 otp_oe OTP device chip-select signal 0x0C otp_sel OTP device write-enable signal 0x10 otp_we...

  • Page 56: Programmed-I/O Sequencing

    Copyright © 2019, SiFive Inc. All rights reserved. 12.3 Programmed-I/O Sequencing The programmed-I/O interface exposes the OTP device’s and power-supply’s control signals directly to software. Software is responsible for respecting these signals' setup and hold times. The OTP device requires that data be programmed one bit at a time and that the result be re- read and retried according to a specific protocol.

  • Page 57: Otp Programming Procedure

    Copyright © 2019, SiFive Inc. All rights reserved. • OTP Memory must be programmed only while the power supply voltages remain within specification. 12.6 OTP Programming Procedure 1. LOCK the otp: a. Write 0x1 to otp_lock b. Check that 0x1 is read back from otp_lock c.

  • Page 58: Always-On (Aon) Domain

    Chapter 13 Always-On (AON) Domain The FE310-G002 supports an always-on (AON) domain that includes real-time counter, a watchdog timer, backup registers, low frequency clocking, and reset and power-management circuitry for the rest of the system. Figure 5 shows an overview of the AON block.

  • Page 59: Aon Power Source

    13.3 AON Reset Unit An AON reset is the widest reset on the FE310-G002, and resets all state except for the JTAG debug interface. An AON reset can be triggered by an on-chip power-on reset (POR) circuit when power is first...

  • Page 60: External Reset Circuit

    The Real-Time Clock is described in detail in Chapter 16. 13.9 Backup Registers The backup registers provide a place to store critical data during sleep. The FE310-G002 has 32 32-bit backup registers. 13.10 Power-Management Unit (PMU) The power-management unit (PMU) sequences the system power supplies and reset signals when transitioning into and out of sleep mode.
  • Page 61 Copyright © 2019, SiFive Inc. All rights reserved. Offset Name Description wdog Configuration 0x000 wdogcfg Counter Register 0x008 wdogcount Scaled value of Counter 0x010 wdogs Feed register 0x018 wdogfeed Key Register 0x01C wdogkey Comparator 0 0x020 wdogcmp0 rtc Configuration 0x040...
  • Page 62 Copyright © 2019, SiFive Inc. All rights reserved. Offset Name Description Sleep program instruction 4 0x130 pmusleepi4 Sleep program instruction 5 0x134 pmusleepi5 Sleep program instruction 6 0x138 pmusleepi6 Sleep program instruction 7 0x13C pmusleepi7 PMU Interrupt Enables 0x140 pmuie...

  • Page 63: Watchdog Timer (Wdt)

    Chapter 14 Watchdog Timer (WDT) The watchdog timer (WDT) is used to cause a full power-on reset if either hardware or software errors cause the system to malfunction. The WDT can also be used as a programmable periodic interrupt source if the watchdog functionality is not required. The WDT is implemented as an upcounter in the Always-On domain that must be reset at regular intervals before the count reaches a preset threshold, else it will trigger a full power-on reset.

  • Page 64: Watchdog Clock Selection

    Copyright © 2019, SiFive Inc. All rights reserved. The counter is incremented at a maximum rate determined by the watchdog clock selection. Each cycle, the counter can be conditionally incremented depending on the existence of certain conditions, including always incrementing or incrementing only when the processor is not asleep.

  • Page 65: Watchdog Compare Register (Wdogcmp)

    Copyright © 2019, SiFive Inc. All rights reserved. dividing the clock rate by , so for an input clock of 32.768 kHz, the LSB of will incre- wdogs ment once per second. The value of is memory-mapped and can be read as a single 16-bit value over the AON wdogs TileLink bus.

  • Page 66: Watchdog Feed Address (Wdogfeed)

    Copyright © 2019, SiFive Inc. All rights reserved. 14.6 Watchdog Feed Address ( wdogfeed After a successful key unlock, the watchdog can be fed using a write of the value 0xD09F00D address, which will reset the register to zero. The full watchdog feed...

  • Page 67: Power-Management Unit (Pmu)

    Chapter 15 Power-Management Unit (PMU) The FE310-G002 power-management unit (PMU) is implemented within the AON domain and sequences the system’s power supplies and reset signals during power-on reset and when tran- sitioning the "mostly off" (MOFF) block into and out of sleep mode.

  • Page 68: Pmu Overview

    Copyright © 2019, SiFive Inc. All rights reserved. 15.1 PMU Overview pm ukey pm usl eep aonr st aonr st sleep PMU State wakeup Countdown 2 Machine done del ay pm upr ogr am pm ucause sleep µPC wakeup µPC...

  • Page 69: Pmu Key Register (Pmukey)

    Copyright © 2019, SiFive Inc. All rights reserved. Offset Name Description Wakeup program instruction 0 0x100 pmuwakeupi0 Wakeup program instruction 1 0x104 pmuwakeupi1 Wakeup program instruction 2 0x108 pmuwakeupi2 Wakeup program instruction 3 0x10C pmuwakeupi3 Wakeup program instruction 4 0x110...

  • Page 70: Initiate Sleep Sequence Register (Pmusleep)

    Copyright © 2019, SiFive Inc. All rights reserved. The PMU output signals are registered and only toggle on PMU instruction boundaries. The out- put registers are all asynchronously set to 1 by aonrst PMU Instruction Format ( pmu(sleep/wakeup)iX Register Offset...

  • Page 71: Pmu Interrupt Enables (Pmuie) And Wakeup Cause (Pmucause)

    Copyright © 2019, SiFive Inc. All rights reserved. signal has a fixed deglitch circuit that requires the signal remain asserted dwakeup dwakeup for two AON clock edges before being accepted. The conditioning circuit also resynchronizes signal to the AON dwakeup lfclk 15.7 PMU Interrupt Enables (...
  • Page 72 Copyright © 2019, SiFive Inc. All rights reserved. Index Meaning Power-on Reset External reset Watchdog timer reset Table 46: Reset cause values...

  • Page 73: Real-Time Clock (Rtc)

    Chapter 16 Real-Time Clock (RTC) The real-time clock (RTC) is located in the always-on domain, and is clocked by a selectable low-frequency clock source. For best accuracy, the RTC should be driven by an external 32.768 kHz watch crystal oscillator, but to reduce system cost, can be driven by a factory- trimmed on-chip oscillator.

  • Page 74: Rtc Configuration Register (Rtccfg)

    Copyright © 2019, SiFive Inc. All rights reserved. rtccounthi: High bits of Counter ( rtccounthi Register Offset 0x4C Bits Field Name Attr. Rst. Description [31:0] High bits of Counter rtccounthi Table 47: rtccounthi: High bits of Counter rtccountlo: Low bits of Counter (...
  • Page 75 Copyright © 2019, SiFive Inc. All rights reserved. rtccmp0: Comparator 0 ( rtccmp0 Register Offset 0x60 Bits Field Name Attr. Rst. Description [31:0] Comparator 0 rtccmp0 Table 50: rtccmp0: Comparator 0...

  • Page 76: General Purpose Input/Output Controller (Gpio)

    This chapter describes the operation of the General Purpose Input/Output Controller (GPIO) on the FE310-G002. The GPIO controller is a peripheral device mapped in the internal memory map. It is responsible for low-level configuration of actual GPIO pads on the device (direction, pull up-enable, and drive value ), as well as selecting between various sources of the controls for these signals.
  • Page 77 Copyright © 2019, SiFive Inc. All rights reserved. Figure 9: Structure of a single GPIO Pin with Control Registers. This structure is repeated for each pin.

  • Page 78: Gpio Instance In Fe310-G002

    Copyright © 2019, SiFive Inc. All rights reserved. 17.1 GPIO Instance in FE310-G002 FE310-G002 contains one GPIO instance. Its address and parameters are shown in Table 51. Instance Number Address ngpio 0x10012000 Table 51: GPIO Instance 17.2 Memory Map The memory map for the GPIO control registers is shown in Table 52. The GPIO memory map has been designed to require only naturally-aligned 32-bit memory accesses.

  • Page 79: Interrupts

    Copyright © 2019, SiFive Inc. All rights reserved. 17.4 Interrupts A single interrupt bit can be generated for each GPIO bit. The interrupt can be driven by rising or falling edges, or by level values, and interrupts can be enabled for each GPIO bit individually.
  • Page 80 Copyright © 2019, SiFive Inc. All rights reserved. GPIO Number IOF0 IOF1 PWM0_PWM0 PWM0_PWM1 SPI1_CS0 PWM0_PWM2 SPI1_DQ0 PWM0_PWM3 SPI1_DQ1 SPI1_SCK SPI1_DQ2 SPI1_DQ3 SPI1_CS1 SPI1_CS2 SPI1_CS3 PWM2_PWM0 PWM2_PWM1 I2C0_SDA PWM2_PWM2 I2C0_SCL PWM2_PWM3 UART0_RX UART0_TX UART1_TX PWM1_PWM1 PWM1_PWM0 PWM1_PWM2 PWM1_PWM3 UART1_RX SPI2_CS0...

  • Page 81: Universal Asynchronous Receiver/Transmitter (Uart)

    The UART peripheral does not support hardware flow control or other modem control signals, or synchronous serial data transfers. 18.2 UART Instances in FE310-G002 FE310-G002 contains two UART instances. Their addresses and parameters are shown in Table 54. Instance Num-...

  • Page 82: Memory Map

    Copyright © 2019, SiFive Inc. All rights reserved. 18.3 Memory Map The memory map for the UART control registers is shown in Table 55. The UART memory map has been designed to require only naturally aligned 32-bit memory accesses. Offset...

  • Page 83: Transmit Control Register (Txctrl)

    Copyright © 2019, SiFive Inc. All rights reserved. Receive Data Register ( rxdata Register Offset Bits Field Name Attr. Rst. Description [7:0] Received data data [30:8] Reserved Receive FIFO empty empty Table 57: Receive Data Register 18.6 Transmit Control Register (...

  • Page 84: Interrupt Registers (Ip And Ie)

    Copyright © 2019, SiFive Inc. All rights reserved. Receive Control Register ( rxctrl Register Offset Bits Field Name Attr. Rst. Description Receive enable rxen [15:1] Reserved [18:16] Receive watermark level rxcnt [31:19] Reserved Table 59: Receive Control Register 18.8 Interrupt Registers (...
  • Page 85 Copyright © 2019, SiFive Inc. All rights reserved. The input clock is the bus clock . The reset value of the register is set to , which tlclk div_init is tuned to provide a 115200 baud output out of reset given the expected frequency of tlclk Table 62 shows divisors for some common core clock rates and commonly used baud rates.

  • Page 86: Serial Peripheral Interface (Spi)

    SPI flash device and instead return immediately. Hardware interlocks ensure that the current transfer completes before mode transitions and control register updates take effect. 19.2 SPI Instances in FE310-G002 FE310-G002 contains three SPI instances. Their addresses and parameters are shown in Table...

  • Page 87: Memory Map

    Copyright © 2019, SiFive Inc. All rights reserved. Instance Flash Controller Address cs_width div_width QSPI 0 0x10014000 SPI 1 0x10024000 SPI 2 0x10034000 Table 64: SPI Instances 19.3 Memory Map The memory map for the SPI control registers is shown in Table 65. The SPI memory map has...

  • Page 88: Serial Clock Divisor Register (Sckdiv)

    Copyright © 2019, SiFive Inc. All rights reserved. Offset Name Description Serial clock divisor 0x00 sckdiv Serial clock mode 0x04 sckmode Reserved 0x08 Reserved 0x0C Chip select ID 0x10 csid Chip select default 0x14 csdef Chip select mode 0x18 csmode...

  • Page 89: Serial Clock Mode Register (Sckmode)

    Copyright © 2019, SiFive Inc. All rights reserved. The input clock is the bus clock . The reset value of the field is tlclk Serial Clock Divisor Register ( sckdiv Register Offset Bits Field Name Attr. Rst. Description [11:0] Divisor for serial clock.

  • Page 90: Chip Select Default Register (Csdef)

    Copyright © 2019, SiFive Inc. All rights reserved. Chip Select ID Register ( csid Register Offset 0x10 Bits Field Name Attr. Rst. Description [31:0] csid Chip select ID. bits wide. Table 70: Chip Select ID Register 19.7 Chip Select Default Register (...

  • Page 91: Delay Control Registers (Delay0 And Delay1)

    Copyright © 2019, SiFive Inc. All rights reserved. 19.9 Delay Control Registers ( delay0 delay1 registers allow for the insertion of arbitrary delays specified in units of delay0 delay1 one SCK period. field specifies the delay between the assertion of CS and the first leading edge of cssck SCK.

  • Page 92: Transmit Data Register (Txdata)

    Copyright © 2019, SiFive Inc. All rights reserved. For flash-enabled SPI controllers, the reset value is , corresponding to 0x0008_0008 proto single, = Tx, = MSB, and = 8. For non-flash-enabled SPI controllers, the reset endian value is , corresponding to...

  • Page 93: Receive Data Register (Rxdata)

    Copyright © 2019, SiFive Inc. All rights reserved. flag indicates whether the transmit FIFO is ready to accept new entries; when set, full writes to are ignored. The field returns when read. txdata data Transmit Data Register ( txdata Register Offset...

  • Page 94: Receive Watermark Register (Rxmark)

    Copyright © 2019, SiFive Inc. All rights reserved. 19.14 Receive Watermark Register ( rxmark register specifies the threshold at which the Rx FIFO watermark interrupt triggers. rxmark The reset value is Receive Watermark Register ( rxmark Register Offset 0x54 Bits Field Name Attr.

  • Page 95: Spi Flash Interface Control Register (Fctrl)

    Copyright © 2019, SiFive Inc. All rights reserved. 19.16 SPI Flash Interface Control Register ( fctrl When the bit of the register is set, the controller enters direct memory-mapped SPI fctrl flash mode. Accesses to the direct-mapped memory region causes the controller to automati- cally sequence SPI flash reads in hardware.

  • Page 96: Pulse Width Modulator (Pwm)

    Chapter 20 Pulse Width Modulator (PWM) This chapter describes the operation of the Pulse-Width Modulation peripheral (PWM). 20.1 PWM Overview Figure 10 shows an overview of the PWM peripheral. The default configuration described here has four independent PWM comparators ( –...

  • Page 97: Pwm Instances In Fe310-G002

    Copyright © 2019, SiFive Inc. All rights reserved. Figure 10: PWM Peripheral 20.2 PWM Instances in FE310-G002 FE310-G002 contains three PWM instances. Their addresses and parameters are shown in Table 88. Instance Number Address ncmp cmpwidth 0x10015000 0x10025000 0x10035000 Table 88: PWM Instances 20.3 PWM Memory Map...

  • Page 98: Pwm Count Register (Pwmcount)

    PWM 3 compare register 0x2C pwmcmp3 Table 89: SiFive PWM memory map, offsets relative to PWM peripheral base address 20.4 PWM Count Register ( pwmcount The PWM unit is based around a counter held in . The counter can be read or written pwmcount over the TileLink bus.

  • Page 99: Pwm Configuration Register (Pwmcfg)

    Copyright © 2019, SiFive Inc. All rights reserved. 20.5 PWM Configuration Register ( pwmcfg PWM Configuration Register ( pwmcfg Register Offset Bits Field Name Attr. Rst. Description [3:0] PWM Counter scale pwmscale [7:4] Reserved PWM Sticky - disallow clearing bits...

  • Page 100: Scaled Pwm Count Register (Pwms)

    Copyright © 2019, SiFive Inc. All rights reserved. The 4-bit field scales the PWM counter value before feeding it to the PWM compara- pwmscale tors. The value in is the bit position within the register of the start of a...

  • Page 101: Deglitch And Sticky Circuitry

    Copyright © 2019, SiFive Inc. All rights reserved. PWM 2 Compare Register ( pwmcmp2 Register Offset 0x28 Bits Field Name Attr. Rst. Description [15:0] PWM 2 Compare Value pwmcmp2 [31:16] Reserved Table 95: PWM 2 Compare Register PWM 3 Compare Register (...

  • Page 102: Generating Left- Or Right-Aligned Pwm Waveforms

    Copyright © 2019, SiFive Inc. All rights reserved. bit disallows the registers from clearing if they are already set and pwmsticky pwmcmp is used to ensure interrupts are seen from the bits. pwmcmp 20.9 Generating Left- or Right-Aligned PWM Waveforms Figure 11: Basic right-aligned PWM waveforms.

  • Page 103: Generating Arbitrary Pwm Waveforms Using Ganging

    Copyright © 2019, SiFive Inc. All rights reserved. This technique provides symmetric PWM waveforms but only when the PWM cycle is at the largest supported size. At a 16 MHz bus clock rate with 16-bit precision, this limits the fastest PWM cycle to 244 Hz, or 62.5 kHz with 8-bit precision.

  • Page 104: Generating One-Shot Waveforms

    Copyright © 2019, SiFive Inc. All rights reserved. 20.12 Generating One-Shot Waveforms The PWM peripheral can be used to generate precisely timed one-shot pulses by first initializing the other parts of then writing a 1 to the bit. The counter will run for one...

  • Page 105: Inter-Integrated Circuit (I²C) Master Interface

    Chapter 21 Inter-Integrated Circuit (I²C) Master Interface The SiFive Inter-Integrated Circuit (I²C) Master Interface is based on OpenCores® I²C Master Core. Download the original documentation at https://opencores.org/project,i2c. All I²C control register addresses are 4-byte aligned. 21.1 I²C Instance in FE310-G002 FE310-G002 contains one I²C instance.

  • Page 106: Debug

    Chapter 22 Debug This chapter describes the operation of SiFive debug hardware, which follows The RISC‑V Debug Specification 0.13. Currently only interactive debug and hardware breakpoints are sup- ported. 22.1 Debug CSRs This section describes the per-hart trace and debug registers (TDRs), which are mapped into...

  • Page 107: Trace And Debug Data Registers (Tdata1-3)

    Copyright © 2019, SiFive Inc. All rights reserved. Trace and Debug Select Register tselect Bits Field Name Attr. Description [31:0] index WARL Selection index of trace and debug registers Table 100: tselect field is a WARL field that does not hold indices of unimplemented TDRs. Even if index can hold a TDR index, it does not guarantee the TDR exists.

  • Page 108: Debug Control And Status Register (Dcsr)

    Debug ROM. The debugger may use it as described in The RISC‑V Debug Specifi- cation 0.13. 22.2 Breakpoints The FE310-G002 supports eight hardware breakpoint registers per hart, which can be flexibly shared between debug mode and machine mode. When a breakpoint register is selected with...
  • Page 109 Copyright © 2019, SiFive Inc. All rights reserved. Breakpoint Control Register ( mcontrol Register Offset Bits Field Attr. Rst. Description Name WARL Address match on LOAD WARL Address match on STORE WARL Address match on Instruction FETCH WARL Address match on User Mode...

  • Page 110: Breakpoint Match Address Register (Maddress)

    Copyright © 2019, SiFive Inc. All rights reserved. breakpoint register giving the address 1 byte above the breakpoint range, and using the chain bit to indicate both must match for the action to be taken. NAPOT ranges make use of low-order bits of the associated breakpoint address register to...

  • Page 111: Sharing Breakpoints Between Debug And Machine Mode

    – 0x300 0x3FF The FE310-G002 has 16 32-bit words of program buffer for the debugger to direct a hart to exe- cute arbitrary RISC-V code. Its location in memory can be determined by executing aiupc instructions and storing the result into the program buffer.

  • Page 112: Debug Flags (0X100-0X110, 0X400-0X7Ff)

    The specific behavior of the flags is not further documented here. 22.3.4 Safe Zero Address In the FE310-G002, the debug module contains the address in the memory map. Reads to this address always return 0, and writes to this address have no impact. This property allows a "safe"...

  • Page 113: Debug Interface

    Chapter 23 Debug Interface The SiFive FE310-G002 includes the JTAG debug transport module (DTM) described in The RISC‑V Debug Specification 0.13. This enables a single external industry-standard 1149.1 JTAG interface to test and debug the system. The JTAG interface is directly connected to input pins.

  • Page 114: Resetting Jtag Logic

    Copyright © 2019, SiFive Inc. All rights reserved. Figure 13: JTAG TAPC state machine. 23.2 Resetting JTAG Logic The JTAG logic must be asynchronously reset by asserting the power-on-reset signal. This dri- ves an internal signal. jtag_reset Asserting resets both the JTAG DTM and debug module test logic. Because parts...

  • Page 115: Jtag Standard Instructions

    The JTAG DTM implements the BYPASS and IDCODE instructions. On the FE310-G002, the IDCODE is set to 0x20000913 23.5 JTAG Debug Commands The JTAG DEBUG instruction gives access to the SiFive debug module by connecting the debug scan register between jtag_TDI jtag_TDO...

  • Page 116: References

    Chapter 24 References Visit the SiFive forums for support and answers to frequently asked questions: https://forums.sifive.com [1] A. Waterman and K. Asanovic, Eds., The RISC-V Instruction Set Manual, Volume I: User- Level ISA, Version 2.2, May 2017. [Online]. Available: https://riscv.org/specifications/ [2] ——, The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10,...

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