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VIDEO SYSTEM BLOCK DIAGRAM (2/2)
IC3001
(DVMAIN)
MAIN
0
1
257
YSO0
YSO3
258
( VBID DET RAM )
193
BRSO0
BRSO3
194
122
OUTH
43
OUTV
5
( CLOCK CONV )
TO
CAMERA DSP
39
INH
a
119
INV
CLK27A
38
OSC27I
TO
CAMERA DSP
b
TO CPU
ADDTO0
67
AD0
AD15
ADDT15
150
DV_RST
64
XRESET
4
CDALE
142
CPUALE
CDWE
212
XCPUDSTB0
CDDSTB
143
XCPUDSTB1
DRWSEL
213
XCPURW
TO
CAMERA DSP
c
DV_WATT
66
CPUWAIT
TO
CPU
d
3
DSC
*1
TO USB
DSYIO0
TO
DSYIO7
CAMERA DSP
DSCIO0
DSCIO7
DSYO0
DSYO7
DSCO0
DSCO7
CLKDSC
HDDSC
VDDSC
2
FLDDSC
R8068
C8026
CLK27B
IC8006
Q8002
CLOCK GEN.
BUFF
DOMCK2
DOBCK2
TO
AU.AD
DOLRCK2
AIDAT2
DSC_WKUP
DSC_CS
DSC_CLK
DSC_DT_OUT
DSC_DT_IN
USBDOWN
DSC_RST
TO
MXDT_OUT
CPU
CAPT_REQ
DSC_STS
MMC_DC
TO
1
D8001
J502
USBSENS
2
IC8004
GIO15
GIO6
GIO3
FLSH_RST
TO
IC8003-12PIN
A
VIDEO I/F
COMPRESS
OUTER ECC
RAM
INNER ECC
( DCT,VLC VLD
( ENC/DET )
( SUB/AUX )
(ENC/DEC)
WORK RAM )
FORMATTER
( Formatting Sync
Detect ID Protect
De-formatting )
RAM
RAM
RAM
RAM
( CLOCK CONV )
( CLOCK CONV )
( CLOCK CONV )
D-RAM I/F
IEE1394
AUDIO
LINK
( WORK RAM
( ISO/
PROGRAM
ASYNC
RISC CORE )
FIFO )
(DECK_DSP)
TO
R3034
JIG CONN
PS_PLL
CN105
D0 D15
16
EM_CS2
IC8001
FLSH_OE
FLSH_WE
A10
246
YIO0
YIO7
CN103
244
174
MMC_DATA
SDI3
2
188
CIO0
173
MMC_CLK
SCK3
5
MMC_CMD
CIO7
250
247
SDO3
7
117
M32_MMC_CS
GIO20
9
191
3
YIN0
YIN7
190
39
16
ARM_D15
237
DSC R/D_DATA
CIN0
ARM_D0
CIN7
108
235
20
7
176
ARM_A19
CLKIN1
DSC R/D_ADRESS
172
ARM_A0
HDIN
20
249
VDIN
212
9
29
45
25
FID
199
MXI
R8022
A0~A19
DQ0~DQ15
239
MXO
219
CLKIN2
IC8003
134
GIO14
( 16M_FLASH RAM )
28
127
EM_CS2
GIO16
26
11
95
EM_CSO
FLSH_CE
DSP_CLKS
85
28
106
EM_OE
FLSH_OE
DSP_BCLKX
9
11
104
EM_WE
FLSH_WE
DSP_BCLKR
12
105
RESET
DSP_BFSX
114
DSP_BFSR
94
FROM
DSP_BDR
IC1001-6PIN
157
X8002
GIO0
49
2
125
GIO18
M48XI
206
3
CXO
30
SCLK1
M48XO
205
SDI1
48MHz
184
15
SDO1
2
SDR_DQ0
DQ0
135
SDRAM_DATA
GIO13
SDR_DQ31
DQ31
182
122
56
RESET
129
25
136
SDR_A0
GIO12
A0
SDRAM_ADRESS
146
SDR_A14
A14
GIO7
149
24
138
IC8002
67
159
GIO11
SDR_CKE
CKE
164
51
68
GIO2
SDR_CLK
CLK
177
20
64M
SDR_CS
CS
18
201
SDRAM
SDR_CAS
CAS
160
71
1
SDR_DQMLH
DQM1
200
19
128
SDR_RAS
RAS
GIO15
195
59
SDR_DQMHH
DEM3
147
17
GIO6
193
SDR_WE
WE
1158
180
16
GIO3
SDR_DQMLL
DQMO
28
178
SDR_DQMHL
DQM2
B
C
182
FSPLLCTL
PWMAUDIO
173
REC_CTL
RECCTL
100
REC_DATA
RECDATA
174
REC_CLK
RECCLK
242
SPA
SPA
240
HID1
TO
HSP
98
CPU
HID
243
TSR
TRKREF
101
FRP
FRREF
168
AGC_OUT
ADVIN0
IC3002
IC3005
11
1
(DVMAIN)
DAAOUT0
AMP+
4
237
2
AMPO
4
FSPLLCTL
DAAOUT1
AMP-
AO5
18
RECCADJ
AO1
19
ATF_GAIN
AO2
106
5
AO6
DISCRI
12
H_GAIN
Q3002
AO11
239
13
H_OFFSET
VCI4185
BUFF
AO12
R3009
R3010
M_VCOCTL
23
PWM27O
R3011
C3024
104
OSC27O
TO
L3007
105
D3001
OP-DRV
OSC27I
C3023
24
CLK27SEL
TO
MONI C
CN762
D
E
2-81
2-82
0
5
PRE/MDA
IC3501
CN110
CN401
HID3
HID3
38
38
3
HID3
PBH
PBH
41
TO
36
5
PB_H
CPU
RECH
RECH
42
35
6
REC_H
HID1
HID1
40
24
37
4
HID1
Y2
REC_CLK
2
4
REC_CLK
9
20
25
REC_CLK
REC_DATA
REC_DATA
7
IC3502
18
23
REC_DATA
REC_CTL
REC_CTL
44
R_CTL
34
7
25
X2
MONI_CHG
MONI_CHG
12
20
8
33
MONI_CHG
X1
(PRE/REC)
TO
JIG CONN
19
(CN105)
Y1
ENV_OUT
ENV_OUT
48
33
8
PB_MONI
ATF_GAIN
ATF_GAIN
60
27
14
ATF_GAIN
AGC_OUT
AGC_OUT
57
30
11
AGC_BUFF_OUT
RECCADJ
RECCADJ
10
19
22
REC_GAIN
REAR UNIT ASS'Y
CN112
V_OUT
1
12
VOUT
*1 WITH DSC MODEL
TO IC1001,IC8001
TO IC3001
TO
IC1001
TO IC4301
F
CN402
HEAD
2F
6
2S
7
1S
3
2
1F
*1
AIDAT2
DOBCK2
DOLRCK2
TO
AU,DA
DOMCK2
PWAD2
AIMCK
AILRCK
AIBCK
TO
AUDIO
AIDAT
AODAT
TPA+
TPA-
TPB+
DV IN/OUT
TPB-
DV
J501
PD_L
AU_CLK
AU_DATA
AUDIO_CS
TO
A_MOTE
AUDIO
L_MOTE
BUZZER
S_SHUT
G
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