LG GCC-4480B Service Manual page 43

92 DQML
112 CASH#/
RWEH#
113 CLK
114 CKE
102~104, RD15~RD0
106~110,
93~94, 96~101
115, 82, RD11~RA0
116~121,
77~79, 81
Audio Output Interface (6)
122 ADGO
127 DACVDD33
126 RO
125 DACVREF
124 LO
123 AUDACVSS
IPLL VCO (2)
163 IPLLVDD33
162 IPLLVSS
HOST Interface (32)
128 DEVSEL
50
3.3V LVTTL output, SDRAM low-byte data output mask control signal, high active.
PSR, For SDRAM application only.
2mA, 4mA, 6mA,
Default : 4mA, slew rate
8mA, 10mA, 12mA,
14mA, 16mA PDR
Column Address Strobe High/RAM Write Enable High. When a
3.3V LVTTL Output,
PSR, 16-bit DRAM is used, this active-low pin functions as Column
address Strobe High for accessing the upper bytes of a two-CAS#
2mA, 4mA, 6mA,
RAM, or as Write Enable High for writng the upper bytes of a
8mA, 10mA, 12mA,
14mA, 16mA PDR two-WE# RAM.
For SDRAM application, this pin is change to DQMH and is used
to as SDRAM high-byte data mask control signal, high active.
Default : 4mA, slew rate
SDRAM clock output. For SDRAM application only.
3.3V LVTTL I/O,
PSR,
Default : 4mA, slew rate.
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
SDRAM clock enable signal output. For SDRAM application only.
3.3V LVTTL Output,
PSR,
Default : 4mA, slew rate.
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
RAM Data Bus. These pins are the bi-directional upper Buffer
3.3V LVTTL I/O,
RAM data bus to the external buffer memory.
PSR, PSMT,
Default : 4mA, slew rate, pull-up, no SMT.
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR,
75K PPU, 75K PPD
RAM Address Bus [11:0].
3.3V LVTTL Output,
Default : 4mA, slew rate.
PSR,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
3.3V LVTTL output, Digital Audio Output. The signal is the Digital Audio Output which
slew rate, supplies the IEC-958 digital audio data.
4mA, 8mA PDR
Default : 2mA.
Analog Power(3.3V) Power supply for internal audio DAC circuitry.
Analog Output Right channel of audio.
Analog Output Reference voltage for external audio filter circuit.
Analog Output Left channel of audio.
Ground Ground pin for internal audio DAC circuitry.
Analog power(3.3V) Power supply for IPLL circuitry.
Ground Ground pin for IPLL circuitry.
3.3V LVTTL Input, Device Select. Cleared to zero indicates the MT1618 is master
SMT, 75K pull-up
device. Set to one indicates the MT1618 is slave device.