LG GCC-4480B Service Manual page 42

EFMPLL VCO (4)
55 EFMPLLVDD33 Analog power(3.3V)
54 EFMVCOCIN
52 EFMPLLVSS
53 EFMLPFGND
Crystal Interface (2)
185 XTALI
184 XTALO
Memory Interface (38)
84 BA1
85 BA0
87 ROE#
88 RAS#
90 CASL#
91 RWE#
Power supply for EFMPLL circuitry.
Analog input EFMPLL VCO input. For external loop filter connection.
Ground Ground pin for EFMPLL circuitry.
Analog input EFMPLL LPF ground input.
Input X'tal input. The working frequency is 33.88688 MHz.
Output X'tal output.
3.3V LVTTL output,
SDRAM bank address 1 signal. When 4-bank SDRAM is used,
PSR,
this pin is used to select bank2 and bank3 space and must
2mA, 4mA, 6mA, connect to "BA1" pin of SDRAM.
8mA, 10mA, 12mA,
When two 2-bank SDRAM are used, this pin is used as "Chip
14mA, 16mA PDR
Select" signal output for second SDRAM and must connect to
"CS#" pin of second SDRAM.
When two DRAM are used, this pin is used as "Row Address
Strobe", signal output for second DRAM and must connect to
"RAS#" pin of second DRAM.
Default : 4mA, slew rate
3.3V LVTTL I/O, SDRAM bank address 0 signal. For SDRAM application only.
PSR, Default : 4mA, slew rate
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
3.3V LVTTL Output,
RAM Output Enable, low active.
PSR,
For SDRAM application this pin is "Chip Select" signal output
2mA, 4mA, 6mA,
connect to "CS#" pin of SDRAM. When two 2-bank SDRAM are
8mA, 10mA, 12mA,
used, this pin must connect to "CS#" pin of first SDRAM.
14mA, 16mA PDR
Default : 4mA, slew rate.
RAM Row Address Strobe. This active -low output is the Row
3.3V LVTTL Output,
Address Strobe signal to the RAM.
PSR,
For SDRAM application, this pin is "row address strobe" signal
2mA, 4mA, 6mA,
output connected to SDRAM.
8mA, 10mA, 12mA,
14mA, 16mA PDR
Default : 4mA, slew rate.
Column Address Strobe Low / Column Address Strobe. When two
3.3V LVTTL Output,
column address strobe pins are used, this pin is the Column
PSR,
Address Strobe Low signal for accessing the lower bytes of a two-
2mA, 4mA, 6mA,
8mA, 10mA, 12mA, CAS# 16-bit RAM. When an 8-bit DRAM is used, this pin shall be
14mA, 16mA PDR connected to CAS# of the DRAM.
For SDRAm apllication, this pin is "column address strobe" signal
output connected to SDRAM.
Default : 4mA, slew rate.
RAM Write Enable/RAM Write Enable Low. RAM write enable
3.3V LVTTL Output,
PSR, signal, low active. When two write enable pins are used, it is the
2mA, 4mA, 6mA, Write Enable Low signal for writing the lower bytes of a two-
WE_16-bit RAM.
8mA, 10mA, 12mA,
14mA, 16mA PDR
For SDRAM application, this pin is dedicated for "Write Enable"
usage.
Default : 4mA, slew rate.
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