HP 8562E Service Manual page 309

Table 8-13. Control Word at Primary Address (U3 and U4) (continued)
Bit Mnemonic
Bit 2 GAINX2
Bit 3 VTRIG-POL
Bit 4 LSAMPLE
Bit 5 LADCEN
LLOADADDR
Bit 6
LLOADPOST
Bit 7
LVTRIG-EN
Bit 8
LREADCLK
Bit 9
State
Turns on X2 log expand amplifier.
1
0
Controls digital video trigger polarity.
1 Negative-edge video trigger.
Positive-edge video trigger.
0
Enables sample detection mode.
1 Sample detection mode disabled.
Sample detection mode enabled.
0
Enables FADC memory for 'Lwrites".
(Toggled in conjunction with bit 0.)
1 Disables FADC memory for "writes".
Enables FADC memory for "writes".
0
Enables load address counter.
1 "Writes" to the address counter disabled.
"Writes" to the address counter enabled.
0
Enables load post-trigger counter.
1 "Writes" to the post-trigger counter disabled.
"Writes" to the post-trigger counter enabled.
0
Enables digital video trigger on A16.
Digital video trigger disabled.
1
0 Digital video trigger enabled.
Clocks counters during "read" mode. Used to load
post-trigger counter or address counter. Also used to
post-increment address counter following memory "reads".
Read clock disabled.
1
Read clock enabled.
0
Description