Jäger ADwin-Pro System And Hardware Description page 119

ADwin
19CNTII1 74LS19
74LS19
HCPL-2631
74LS19
Sub-D-
19/37 18/36 17/35
Pin-Nr.:
74LS19
74LS19
HCPL-2631
74LS19
Sub-D-
Pin-Nr.: 11/29 10/28 9/27
74LS19
OCX
Sub-D-Pin-Nr.: 20/1
Fig. 217 – Pro-CNT-16/16-I Rev.
Counter
Counter resolution
Event input
Input current
input voltage range
(selectable via jumpers)
Switching threshold for 0-low
Switching threshold for 1-high
Input resistance
Input over-voltage
Switching time
Connector
Isolation
Fig. 218 –
ADwin-Pro Hardware, manual version 2.9, June 2006
19CNT01
74LS19
HCPL-2631 HCPL-2631 HCPL-2631
FPGA FPGA
16/34 15/33 14/32 13/31 12/30
74LS19
74LS19
HCPL-2631 HCPL-2631 HCPL-2631
8/26 7/25 6/24 5/23 4/22
FPGA FPGA
HCPL-2631
ON
1 2 3 4 5 6 7 8
A0 A1 A2 A3 A4 A5 A6 A7
A: Board and front panel
16 up counters
16 bit
1
typ. 7mA / max. 15mA
0...5V
0...0.8V
4.5...5V
560 Ω
-5V ... 8V
200ns
37-pin DSub socket
42V channel-channel / channel-GND
Pro-CNT-16/16-I Rev.
Pro I: Digital-I/O- and Counter Modules
CNT-16/16-I
COUNTER
0 ... 12V 0...24V
0...1.6V 0...3.2V
10...12V 20...24V
2 kΩ 4.3 kΩ
-5V ... 16V -5V ... 30V
A: Specification
Pro-CNT-16/16-I Rev. A
INPUT
115