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3.4.1 GENERAL INFORMATION: This subsection gives
a component-level technical description of the game's elec
tronic circuitry. Drawing number 003750 is a two-sheet
schematic diagram of the circuitry on the printed circuit
board, and drawing number A003750 is the PCB assembly
drawing showing the locations of the components called
out on the schematic. The position of each integrated
circuit device is identified by a column letter designation
(A through P). and by a row number designation (1 through
9). Drawing number 003266 is a schematic of the harness
wiring inside the game cabinet. These drawings and a sche
matic diagram of the TV monitor's circuitry are included in
Section VII of this manual.
On the PCB schematic the symbol
various inputs to logic gates and other integrated circuits)
indicates a connection to +5 volts through a pull-up resistor.
In the subsections that follow, the portions of the
circuitry being described can be located on the PCB sche
matic by finding the intersection of the zone letters (A, B,
C or D) and the zone numbers (1 through 8). For example,
the designation sheet 1, zone A 8 refers to the extreme
lower left corner of sheet 1 of the schematic.
The output from a 12-MHz crystal-controlled oscillator at
L4 pin 1 is divided by 2 at flip-flop Kl pin 2. The 6-MHz
signal produced at K 1 pin 5 is then used as the
main system clock. From every 384
at Kl pin 11, the configuration formed by flip-flop Kl and
gate K2 passes a partial string of 255 consecutive clock
pulses in each horizontal line at K2 pin 10. By additional
gating at M 1 pins 10, 2, 4 and 12, the
4 signals are generated. Their relationship to other
timing signals associated with the horizontal scan lines seen
on the TV screen is ,hown in the timing diagram of Figure
3-2. The
1 through
clock the horse motion counters (see para. 3.4.7).
SYNCHRONIZATION INFORMATION (SHEET 2,
ZONES C 6, 7, 8 and D 6, 7, 8): Flip-flop H2 (with output
at pin 5) and typc-9316 counters H 1 and Fl compri,e a
horizontal sync chain which divides the
384. The timing relationships between the
and
chain arc shown in Figure 3-2. The
10 is the basis for the horizontal synchronization informa
tion sent to the TV monitor, and the
pin 9 is the basis for the horizontal component of the video
blanking information to the monitor.
10
3.4 DETAILED TECHNICAL DESCRIPTION
OF OPERATION
3.4.2 CLOCK SIGNALS (SHEET 2, ZONES D 6, 7, 8):
CLOCK
HCLOCK
HCLOCK
3.4.3 GENERATION OF HORIZONTAL
HSYNC, FINISH LINE
P (appearing at
pulses applied
1 through
4 signals arc used to
signal by
signals produced in this
signal at J2 pin
signal at H2
CLOCK
HCLOCK
1-JCLOCK
CLOCK
HBLANK,
HRESE1·
HSYNC
HBLANK
ZONES B 6, 7, 8 and C 6, 7, 8): Flip-flop C2 and type-
9316 counters C3 and D3 comprise a vertical sync chain
which divides the
signal by 272. The circuit con
figuration formed by transistor Q5 and flip-flop E2 detects
power failures and produces a correct start-up sequence on
the vertical sync chain after power is applied. The
signal at J2 pin 13 is the basis for the vertical synchroniza
tion information sent to the TV monitor. The VBTAf.fK
signal at E3 pin 5 is the basis for the vertical component
of the video blanking information to the monitor. The
timing relationships between
with certain other timing signals, is shown in Figure 3-3. A
total of 272
pulses are generated, and thus 272
horizontal scan lines appear on the TV screen, between
successive
signals.
(SHEET 2, ZONES B 6, 7, 8): Flip-flop C2 and type-9316
counters A2 and B2 comprise the racetrack horizontal
motion counter. The
derived directly from the system clock at L 1 pin 12 (in
zone D7), provides the clocking. The counter normally
advances to a count of 384, but occasionally it is forced
to 383 instead. The 383 count is regulated by the
signal at D2 pin 6, a signal derived from the type-
9316 counter in location PS. This counter acts as a variable
rate pulse generator that is programmed by the A, A, B
and C signals (applied at P5 pins 6, 5, 4 and 3) to divide by
an increasingly smaller number. The A, A, B and C signals
come from the leader detection circuit (see para. 3.4.8) and
represent the position of the leading player's horse along
the racetrack. As the leading horse gets closer and closer to
the finish line, counter PS goes through its cycle at a
faster and faster rate and the broken-line racetrack is made
to move faster and faster from right to left across the TV
screen.
(SHEET 2, ZONES A 7 and 8): The picket information on
the TV screen is derived from the
produced at B1 pin 15. The type-9316 device in location
B1 is configured to act as a programmable one-shot that
is triggered at regular intervals along the racetrack by the
signal coming from Dl pin 8. But B 1 's output at pin 15
times out after the random length of time determined by
its position along the racetrack and a random number coming
from A 1 pin 8. The shift register device in location Al cir
culates the random number until the picket is off the TV
screen, at which time another random number is loaded
from F 4 pin 3 so that the new pickets follow a random
pattern. This design insures that the spacing between suc
cessive pickets on the screen will be irregular. The shift
3.4.4 GENERATION OF VERTICAL
SYNCHRONIZATION INFORMATION (SHEET 2,
HSYNC
HSYNC
VSYNC
3.4.5 GENERATION OF RACETRACK INFORMATION
BUFFERED CLOCK
CLOCK
3.4.6 GENERATION OF PICKET INFORMATION
and
and
signal, which is
signal
VSYNC
VSYNC
VBLANK,
TRACK
PICKET LI NE
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