XESS XStend Manual page 9

Jumper
J16
J17
Here are the connections from the XS40 and XS95 Boards to their own RAMs and the RAMs of
the XStend Board (expressed as UCF constraints):
Listing 9: Connections between the XStend RAMs and the XS40.
NET AD0
NET AD1
NET AD2
NET AD3
NET AD4
NET AD5
NET AD6
NET AD7
NET A0
NET A1
NET A2
NET A3
NET A4
NET A5
NET A6
NET A7
NET A8
NET A9
NET A10
NET A11
NET A12
NET A13
NET A14
NET A15
NET WR_
NET OE_
NET CE_
NET LCE_
NET RCE_
Listing 10: Connections between the XStend RAMs and the XS95.
NET AD0
NET AD1
NET AD2
NET AD3
NET AD4
NET AD5
Table 2: Jumper settings for XStend RAMs.
Setting
Removing the shunt on this jumper disables the left
RAM U5 by pulling its chip-select pin high.
Removing the shunt on this jumper disables the right
RAM U6 by pulling its chip-select pin high.
LOC=P41; # DATA BUS
LOC=P40;
LOC=P39;
LOC=P38;
LOC=P35;
LOC=P81;
LOC=P80;
LOC=P10;
LOC=P3; # LOWER BYTE OF ADDRESS
LOC=P4;
LOC=P5;
LOC=P78;
LOC=P79;
LOC=P82;
LOC=P83;
LOC=P84;
LOC=P59; # UPPER BYTE OF ADDRESS
LOC=P57;
LOC=P51;
LOC=P56;
LOC=P50;
LOC=P58;
LOC=P60;
LOC=P28;
LOC=P62; # ACTIVE-LOW WRITE-ENABLE FOR ALL RAMS
LOC=P61; # ACTIVE-LOW OUTPUT-ENABLE FOR ALL RAMS
LOC=P65; # ACTIVE-LOW CHIP-ENABLE FOR XS40 RAM
LOC=P7; # ACTIVE-LOW CHIP-ENABLE FOR LEFT XSTEND RAM
LOC=P8; # ACTIVE-LOW CHIP-ENABLE FOR RIGHT XSTEND RAM
LOC=P44; # DATA BUS
LOC=P43;
LOC=P41;
LOC=P40;
LOC=P39;
LOC=P37;