XESS XStend Manual page 18

010- clk
011- hsync_
012- vsync_
013- red1..red0
014- green1..green0
015- blue1..blue0 PIN ISTYPE 'REG';
016- a14..a0
017- ad7..ad0
018- ce_
019- oe_
020- wr_
021- "------ internal storage and signals -------
022- hcnt8..hcnt0
023- vcnt9..vcnt0
024- pixrg7..pixrg0
025- video_blank
026- delayed_blank
027- "------ synonyms for various items -------
028- hcnt = [hcnt8..hcnt0];
029- vcnt = [vcnt9..vcnt0];
030- vram_addr = [a14..a0];
031- vram_data = [ad7..ad0];
032- pixrg = [pixrg7..pixrg0];
033- pixel = [pixrg3..pixrg0];
034- rgb = [red1..red0,green1..green0,blue1..blue0];
035- X = .X.;
036-
037- EQUATIONS
038-
039- @CARRY 1;
040-
041- rst = 1;
042-
043- hcnt.ACLR = !push_reset_; "clear counter on active-low reset
044- vcnt.ACLR = !push_reset_; "clear counter on active-low reset
045- hcnt.CLK = clk;
046- vcnt.CLK = hsync_;
047-
048- hsync_.ASET = !push_reset_;
049- vsync_.ASET = !push_reset_;
050- hsync_.CLK = clk;
051- vsync_.CLK = hsync_;
052-
053- "column counter rolls-over after 379
054- WHEN (hcnt<380) THEN hcnt:=hcnt+1 ELSE hcnt:=0;
055- "horiz sync is low during this interval to signal the start of new line
056- WHEN ((hcnt>=291)&(hcnt<337)) THEN hsync_:=0 ELSE hsync_:=1;
057- "horizontal counter rolls-over after 524
058- WHEN (vcnt<524) THEN vcnt:=vcnt+1 ELSE vcnt:=0;
059- "vert sync is low during this interval to signal the start of a frame
060- WHEN ((vcnt>=492)&(vcnt<494)) THEN vsync_:=0 ELSE vsync_:=1;
061- "blank video outside of visible region: (0,0)->(255,479)
062- WHEN ((hcnt>=256)#(vcnt>=480)) THEN video_blank=1 ELSE video_blank=0;
063-
064- "video RAM control signals
065- ce_ = 0;
066- oe_ = video_blank; "enable the RAM output when video is not blanked
067- wr_ = 1;
068- "the video RAM address is built from the bits 8-1 of the vert line cnt
069- "and bits 7-1 of the horiz column cnt.
PIN;
PIN ISTYPE 'REG'; "horizontal sync
PIN ISTYPE 'REG'; "vertical (frame) sync
PIN ISTYPE 'REG'; "red component
PIN ISTYPE 'REG'; "green component
PIN;
PIN;
PIN;
PIN;
PIN;
NODE ISTYPE 'REG'; "horizontal column counter
NODE ISTYPE 'REG'; "vertical line counter
NODE ISTYPE 'REG'; "byte register for four pixels
NODE ISTYPE 'COM'; "video blanking signal
NODE ISTYPE 'REG'; "delayed video blanking signal
" keep uC in reset state so it doesn't interfere
"horiz cnt increments on each dot clk
"inc vert line cnt after every horizontal line
"enable the RAM
"disable writing to the RAM
"VGA dot clk
"blue component
"address into video RAM
"data from video RAM
"video RAM chip select
"video RAM output enable
"video RAM write enable
Each RAM byte contains two