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Shuttle HOT-433 User Manual

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  • Page 3 NOTICE /995. Copyrighl All Right Reserved Manual Version Rev All information documcntalion, and specifications contained in lhis manual are subject to change without prior notification by the manufacturer. thor assumes no rejponsibility for any errors or ommissions which may appear in lhis document nor does it make a commitmellf lo update the information coutained herein TRADEMARKS UAt/C...

  • Page 4: Table Of Contents

    TABLE OF CONTENTS PREFACE ....................CHAPTER 1 INTRODUCTION ..............Specif i cation ....4 ................6 Block Diagram ........7 433 Mainboard Description 433 Mainboard Placement ....

  • Page 5: Preface

    Preface HOT-433 main board is a highly integrated IBM PC/ AT compat­ ible system board designed to accommodate 25MHz to 1 OOMHz 486 processors, and features h igh-performance secondary cache memory architecture from 1 28KB up to 1024KB. HOT-433 mainboard features four PCI (Pherpherial Component Interconnect) local bus and four ISA (Industry Standard Architec­...

  • Page 6: Chapter 1 Introduction

    Specification CPU Function 0 CPU clock: 2 5/33/40/50/66/80/ 1 00 MHz 0 Supports Intel 486SX/DX/2DX2/DX4, AMD Am486DX/DX2/DX4, Cyrix Cx486S/DX/DX2, and UMC US CPU 0 Supports S-Series CPU Chipset 0 UMC 888 1 F/8886AF and 8663AF 0 Supports internal and external write back cache 0 Supports PC! master and slave up to 3 3 M Hz 0 Supports PC! burst mode access to local memory Memory...
  • Page 7 Power Management Function 0 Provides four power management modes : On, Doze, Sleep, and Suspend 0 Supports M icrosoft APM 0 Provides EPMI (External Power Management Interrupt) Expansions 0 32-bit PCI bus x 4 16-bit ISA bus x 4 0 2-channel PCI enhanced I DE port Supports up to 4 IDE drives Supports 32 and 1 6-bit data transfers Supports buffers that operate read prefresh and write...

  • Page 8: Block Diagram

    Block Di agram L2 Cache UM8881 F DRAM PCI Bus Master Slots PCI Bus UM8886AF Floppy ISA Bus Slots ISA Bus Parallel & 8002 Serial XD Bus CMOS Keyboard BIOS •6 User's Manual...

  • Page 9: 433 Mainboard Description

    433 Main board Description The major components of 433 maniboard are illus­ trated and described to t h e right a n d b e l o w . Please take a m inute to become fami liar with the board design.
  • Page 10 4. Main Memory 433 mainboard features four 72-pin SIMM (Single In-line Memory Module) sockets organized into four banks, which allow flexible memory configuration and expansion. It may use MB, 2MB, 4MB, 8 MB, 1 6MB, 32MB, and 64M B SIMM to expand memory from 1 MB to 256MB.

  • Page 11: 433 Mainboard Placement

    12. System BIOS 433 mainboard is equipped with AMI system WinBIOS. The NCR 5 3 C 8 1 0 and Adaptec AHA-7850 SCSI B IOS is bu ilt- in with a particulary designed to offer optimum performance of the mainboard. 13.
  • Page 12 433 Main board Placement Memory Bank " "' Cache Bank 0 "'"'"'"'" ""'' ...., �� :!'J;!�� � Cache Bank I ::::::::::::::::::: CIIID CI IID CIXIUI IID mP·�& SOCKET • 1 0 Us er's Manual...

  • Page 13: Chapter 2 Jumper Setting

    Jumper Setting System Clock Selecti on 433 mainboard features a clock generator to pro­ External vide adjustab le system Keyboard BIOS clock frequency. JP l, JP3 I• ••I JP2, and JP3 are all 3-pin jumper which determine the clock frequency. Proper jum per settings for generating 25 MHz to 50MHz clock frequency...

  • Page 14: Cpu Type Selection

    CPU Type Selecti on 433 mainboard accepts any member of the 486 series m icropro­ cessors. If you try to install or upgrade the CPU, you must set the CPU type jumpers accordingly. Note : It is highly recommen ded that a CPU coolin g fan is attached to the CPU to ensure s ys tem s tability .
  • Page 15 lntei486SX IJPI7 JP20 I JPI95 I JP21 JP23 • I JP26 JP28 JP30 • � • • • • ..[IT] I JP25 JP32 JP31 I JP27 JP29 Intel 486SX S-Series 1JPl7 JP20 1 JP19 5 1 JP21 JP23 V>=ti"' 1 JP26 JP28...
  • Page 16 lntei486DXIDX21DX4 S-Series AMD Enhanced Am486 I JP 1 7 JP20 ;:§ . • IJPI95 lJP2l JP23 t.n!:t;O'\ I JP26 JP28 JP30 • • • • I JP25 JP27 JP29 JP31 J P32 Intel 486DX4 (P24C) & AMD Enhanced Am486 Clock Multiplier- JP18 For 3 .
  • Page 17 Intel P24D I JP17 JP20 • • I JP19 5 l JP21 JP23 • JP24 I JP26 JP28 JP30 1!!! !!1 I • • • • • • • ••• JP25 1 JP27 JP32 JP29 JP31 Intel P24D Internal Cache Line JP24 Intel P24D CPU Cache...
  • Page 18 AMD 486DXIDX2/DX4 - IV I JPI7 JP20 ' if' I JP I9 5 IJP21 JP23 '" • • l!ii!i i!l I JP26 JP28 JP30 I JP25 I JP27 JP29 JP31 JP32 AMD Am486DX4-100/DX2-80 Clock Multiplier - JP24 For AMD 3 . 3 V Am486DX4- 00 and Am486DX-80 CPU, I JP24 !"...
  • Page 20 UMC 486S U5 1 JP17 1 JP20 � 1 JP19 5 I JP21 JP23 v.:=t;o- 1 JP26 JP28 JP30 l!iii iil • • JP25 I JP27 JP29 JP31 JP32 • 18 User's Manual...

  • Page 21: Cpu Voltage Selection

    CPU Voltage Selection For Intel 486DX4, AMD Am486DX2-80/DX4- l 00, and Cyrix Cx486DX2-66/DX2-80 CPU, 433 main board features single volt­ age regulator to generate the voltage for CPU (Vee) from 5V to 3.3/3.45/3.6/4.0¥. JP9, JP 1 5, and JPI6 are provided for voltage setting between 5V and 3.3/3.45/3.6/4 .0¥.

  • Page 22: Cache Size Selection

    Cache Si ze Selection 433 mainboard supports exter­ nal cache m e mory s izes of 1 28KB, 2 56KB, 5 1 2KB, and I MB Cache memory is popu­ lated by eight Data SRAM and one Tag S R A M . C ac h e memory is organized into two banks, w ith four S RAM as­...
  • Page 23 • • KB Cache Memory BankO Bank Cacheable Range Cache Tag RAM Data RAM Data RAM Size Write-Through Write-Back U15, 16, 17, 18 U27, 28, 29, 256KB 64K x 8 Empty 32K x 8 64 MB 32MB • • KB Cache Memory •...

  • Page 24: Flash Eeprom Vpp Selection

    Flash EEPROM Vpp Selection 433 mainboard supports both 1 2 V and 5 V programm ing voltage flash EEPROM for system BIOS. JP8 is provided to accommodate these two types of flash EEPROM. for 5V OPEN, Pin 2 3 Close for 1 2V Pin 1 2 Close...

  • Page 25: Chapter 3 Memory Configuration

    Memory Configuration 433 mainboard provides great flexibi l ity to support a number of different on-board memory configurations. Memory SlMM sockets are organized into four banks, with one S l MM socket assigned to each memory banks. 433 mainboard supports 1 MB, 2MB, 4MB, 8MB, 1 6MB, 32MB, and 64MB 72- pin SlMM modules.
  • Page 26 Memory Configuration Reference Table (Cont'd) BANK BANK BANK BANK TOTAL 32MB NONE NONE NONE 32MB 32MB 32MB NONE 64MB NONE 32MB 32MB 32MB NONE 96MB 32MB 32MB 32MB 32MB 128MB 64MB NONE NONE NONE 64MB 64MB 64MB NONE NONE 128MB 64MB 64MB 64MB...

  • Page 27: Chapter 4 Power Management

    Power Management 433 mainboard provides four power management modes for re­ ducing power consumption : On, Doze, S leep, and Suspend. When entering each power management mode, 433 mainboard gener­ ate a distinguishable flashes via the turbo-LED. 433 main board also provide EPMI and power supply power down connector to enchanced power management.

  • Page 28: Power Management Modes Indicator

    Power M anagement Modes Indicator Normally the (Turbo-LED) act as the turbo LED. But "LED 1" when system goes into power management mode, the LED will flashes to indicate the status of the power management modes. a. In (Normal) mode, turbo-LED act as a turbo/normal indicator.

  • Page 29: Chapter 6 Bios Setup

    BIOS Setup configures system information that is stored in CMOS RAM . WinBIOS Setup offers an easy to use graphical user inter­ face that is similar to Microsoft Windows GUI . WinBIOS Setup sets a new standard in BIOS user interfaces. Starting WinBIOS Setup As POST executes, the following message appears : Hit <DEL>...

  • Page 30: Bios Setup Feature

    BIOS Setup Feature The WinBIOS Setup main menu, shown bel o w, is organized into four w indows. Each window corresponds to a section in this chapter. � A ... rioan AHtBJOS S•h\P .._gat.a-.nb <C>J.�,4 .. AMe.l'lc-.n Mrga.trend!l Inc. AdYanc•d Chlpsrt De-teotMaster �t ..
  • Page 31 Default This section has three icons that permit you to select a group of settings for all WinBIOS Setup options. Each WinBIOS Setup option has two default settings. These settings can be applied to all WinBIOS Setup options when you select the Default section on the WinBIOS Setup main menu.

  • Page 32: Using The Keyboard With Winbios Setup

    Using the Keyboard with Win BIOS Setup WinBIOS Setup has a built-in keyboard driver that uses simple keystroke combinations : Keystroke Function <Tab> Move to the next window or field. right, ¢ ¢:> if {} Move to the next field to the left, above, or below.

  • Page 33: Standard Setup

    Standard Setup Stancla:rcl The WinBIOS Standard Setup option described in this section are selected by choosing the approprite high-level icon from the WinBIOS Setup main menu selection screen. The selection win­ dow follows. A�W:toiONt AHIBIOS Setup <C>J.�94 A-:rinn.n H•gatrend.s In<:�. a..t sr •tHnds utu 1 tv Date and Time Configuration...
  • Page 34 that lists all valid disk drive types is displayed. Se­ lect the correct type and press <Enter>. If the hard Slave Disk disk drive is an IDE drive, select Detect Master from the Utility section of the WinBIOS Detect Slave Setup main menu to allow WinBIOS to automati­...

  • Page 35: Advanced Setup

    Advanced Setup Advanced The WinBIOS Advanced Setup options d e scribed in this section are selected by choosing the appropriate high-level icon from the WinBIOS Setup main menu. The selection window is shown below. AMIBIOS SeiuF <Cll!J94., AM�rican .-gat:rends Inc. : Htm�7 1 .
  • Page 36 Mouse Support When this option is enabled, WinBIOS supports a PS/2-type mouse. The settings are Enabled or Disabled. Above 1MB Memory Test When this option is enabled, the WinBIOS memory test is per­ formed on all system memory. When this option is disabled, the memory test is done only on the first I MB of system memory.
  • Page 37 System Boot Up CPU Speed This option sets the speed of the CPU at system boot up time. The settings are High or Low. External Cache This option enables or disables the external cache (L2) memory. The settings are Enable or Disable. Internal Cache This option enables or disables the internal cache memory in the 486 processor.

  • Page 38: Advanced Setup Defaults

    Advanced Setup Defaults BIOS Default OptiMal Fai !-safe Present Present System Keyboard YGA/EGA VGA!EGA Primary Display Mouse Support Disabled Disabled Disabled Above I MB Memory Test Disabled Enabled Enabled Memory Test Tick Sound Extended BIOS RAM Area 0:300 0:300 System Boot Up Num Lock Enabled Disabled Floppy Drive Seek At Boot...

  • Page 39: Chipset Setup

    Chipset Setup Chipset The WinB IOS Chipset Setup options described in this section are selected by choosing the appropriate h igh-level icon from the WinB IOS Setup main menu. The selection w indow is shown below. A"IBJOS St!HUP .*-. rtcan �M.-g•t-...
  • Page 40 Cache Speed Options This option sets the cache burst read/write cycle. The optimal setting depends on system clock speed. The settings are2-l-2, 2- · 2-2, 3-1-3, or 3-2-3. DRAM Read Wait State This option sets the memory read wait state. The optimal set­...
  • Page 41 Video BIOS Cacheable This options sets the video BIOS in the COOO-C7FF area to be cacheable or non-cacheable. The settings are En abled or Dis­ abled. Host-to-PCI Post Write W / S This option sets the Host to PCI post write (CPU bus) wait state of the main board.

  • Page 42: Chipset Setup Defaults

    Chipset Setup Defaults BIOS Default Fai l -safe OptiMal Auto Configuration Function Enabled Disabled 2 - 2 - 2 Cache Speed Options Not adjustable DRAM Read Wait State Not adjustable 2 W. S. DRAM Write Wait State Not adjustable 2 W. S. PC ICLK-to- ISA SYSCLK Divsor Not adjustable PCICLK/4...

  • Page 43: Power Management Setup

    Power M anagement Setup Power Mg,.. t The WinBIOS Power Management Setup options described in this section are selected by choosing the appropriate high-level icon from the WinBIOS Setup main menu . The selection win­ dow is shown below. AMIBJOS Setup <C>19c94 f\toWric�n M•md:r-tt n c\s Inc .
  • Page 44 Suspend Mode Timeout This option sets the timeout length when the mainboard enters mode. The settings range from 2 min to 512 min SUSPEND Disabled. VGA Power Down This option sets the blanking of the display screen when the mainboard enters the mode.
  • Page 45 Monitor IDE Activity This option cal ls for monitoring of the activity of the IDE. timer will start counting, if when there is no activity. Enabled, The settings are En abled or Dis abled. Monitor FLP Activity This option calls for monitoring of the activity of the (Floppy controller).

  • Page 46: Power Management Setup Defaults

    Power Management Setup Defaults BIOS Default OptiMal ra i l -safe Power Management Disabled Disabled APM Function Enabled Disabled Doze Mode Timeout 1 5sec 2M in Sleep Mode Timeout 4 M in Disabled Suspend Mode Timeout 8Min Disabled VGA Power Down Disabled Disabled HOD Power Down...
  • Page 47 BIOS Default OptiMal rai l - s afe Disabled Disabled Monitor I RQ \ 0 Disabled Disabled Monitor IRQ9 Disabled Disabled Monitor IRQ8 Disabled Disabled Monitor I RQ7 Disabled Disabled Monitor IRQ6 Disabled Disabled Monitor IRQ5 Disabled Disabled Monitor IRQ4 Enabled Disabled Monitor IRQ3...

  • Page 48: Peripheral Setup

    Peripheral Setup IE!� Per iphera l The WinBIOS Peripheral Setup options described in this section are selected by choosing the appropriate high-level icon from the WinBIOS Setup main menu. The selection window is shown below. A"fBIOS S�tup Inc, (C)1974,. III M« r-i.G&n Mega.t.,.. n a. PCI OnBoard IDE This option sets the PCI on-board 2-channel IDE controller to be enabled or disabled.
  • Page 49 PCI IDE IRQ This option sets the PCI IDE I RQ triggered mode. The settings are Edge or Level. (This feature only affect PCI I DE add-on card) PCI Primary IDE IRQ This option sets the PCI Primary IDE IRQ. The settings are INTA, INTB, INTC, or INTD.
  • Page 50 Second ary Ctrl Drives Present This option sets the number of the IDE hard disk that is con­ nected to secondary channel port. If the IDE device c· o nnected to this port is other than the hard disk, please do not enter the The options are 1 , 2, and Disabled.

  • Page 51: Peripheral Setup Defaults

    Peripheral Setup Defaul ts BIOS Default Fai l -safe OptiMal PCI OnBoard I DE Enabled Disabled PCI Onboard Secondary IDE Enabled Disabled PCI OnBoard IDE Speed Mode Disabled Disabled PCI IDE Card Present on Auto Auto PCI I DE I RQ Edge Level PCI Primary IDE IRQ...

  • Page 52: Win Bios Password Support

    Win BIOS Password Support Passwo:rd WinBIOS Setup has an optional password feature. The system can be configured so that the users must enter a password every time the system boots or when WinBIOS Setup is executed. The following screen appears when you select the password icon. A'"-rtc41Ul JII J'U BJOS .:;,.
  • Page 53 .:.. •.io.n AMlBJOS Set.u.p "'!'!�•-nels D I!I II II:I EI I'I IJ S e t U s e 'r Pou;'!>word. Select the Password icon from the Security section of Win B I OS main menu. Enter the password and press <Enter>. The screen will not display the characters entered.

  • Page 54: Memory Map

    Appendix MEMORY MAP The fol lowing table shows the use of the fiirst megabyte of memory. Codes Description Length 000000 - 0002 FFh BIOS lntenupt Vector Table 768 bytes BIOS Stack Area 000300 - 0003FFh 256 bytes 000400 - 0004FFh BIOS Data Area 256 bytes Applications Memory, used by the operating system,...

  • Page 55: I/O Map

    I/O MAP [000-0 I F] DMA controller (Master) [020-02 1 ] INTERRUPT control ler (Master) [022-02 3 ) CHIPSET control registers 1/0 Ports [040-0SF] TIMER control registers KEYBOARD interface controller (8042) [060-06F] [070-07F] RTC ports ·and C MOS I/0 ports [080-09F] DMA register [OAO-OBF]...

  • Page 56: Timer Map

    TIMER MAP System timer interrupt TIMER Channel TIMER Channel DRAM REFRESH request TIMER Channel SPEAKER tone generator DMA CHANNEL MAP DMA Channel - 0 Available DMA Channel IBM SDLC FLOPPY DISK adapter DMA Channel DMA Channel Available DMA Channel Cascade for DMA controller 1 Available DMA Channel - 5 DMA Channel...

  • Page 57: Interrupt Map

    INTERRUPT MAP N M I Parity check System TIMER interrupt from TIMER-0 KEYBOARD controller Cascade for I RQ 8- 1 5 SERIAL port 2 SERIAL port I PARALLEL port 2 FLOPPY DISK adapter PARALLEL port I RTC clock Available Available Available Available MATH coprocessor...

  • Page 58: Error Beeps And Message

    Error Beeps and Message Error can occur during POST (Power On Self Test), which is performed every time the system is powered on. Fatal errors are communicated through a series of audible beeps. All errors ex­ cept Beep Code 8 are fatal errors. Fatal errors do not allow the system to continue the boot process.

  • Page 59: Amffiios Post Checkpoint Codes

    AM/BIOS POS T Checkpoint Codes POST is performed by the BIOS when the system is reset or rebooted. POST performs diagnostics tests on system parts and initialized key system components. When a POST routine com­ pletes, a code is written to 1/0 port address SOh. Display this code by attach ing diagnostic equipment to port SOh.
  • Page 60 Codes Description Initial ization after the keyboard controller BAT command is done. The keyboard command byte will be written next. I Oh The keyboard con toller command byte has been written. Issuing the keyboard controller pin 23 and 24 blocking the unblocking command next.
  • Page 61 Codes Description The monochrome and color modes have been set. Toggling parity before the optional video ROM test. Finished toggling parity. Passing control for required configuration before optional video ROM check. Processing before video ROM control is done. Searching for optional video ROM and passing control to this ROM, if present.
  • Page 62 Codes Description Pattern written in base memory. Determining the amount of memory I MB below memory. Amount of memory below 1 MB f ound and verified. Determining the amound of memory above MB next. Amount of memory above MB f ound and verfied. Checking f or soft reset and clearing the memory below MB for a soft reset.
  • Page 63 Codes Description The DMA controller 2 base register test passed. Programming DMA controllers I and 2 next. DMA controllers I and 2 have been programmed. Initializing the 8259 interrupt controllers next. 8259 initial ization has completed. Starting the keyboard test next. The keyboard test has started.
  • Page 64 Codes Description The hard disk controller has been reset. The floppy drive will be con figured next. 9 1 h Floppy configuration is complete. Hard disk configuration will be done next. Hard disk configuration has complete. Setting the base and extended memory sizes next.
  • Page 65 Codes Description The keyboard typematic rate has been set. Programming the memory wait states next. The memory wait states have been programmed. Clearing the screen and enabling parity and the N MI next. A 7h The NMI and parity have been enabled. Performing any required initial ization before passing control to the adaptor ROM at EOOOOh next.
  • Page 66 FCC Notice: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 1 5 of FCC Rules. These l im its are designed to provide reasonable protection against harmfu l interfer­ ence in a residential installation.

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