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Curtiss-Wright FibreXtreme SL100 Hardware Reference Manual

Pci and pmc cards
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SL100/SL240
Hardware Reference
for PCI and PMC Cards
Document No. DDOC0076-000-AN
F-T-MR-S2PCIPMC-A-0-AN

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  • Page 1  SL100/SL240 Hardware Reference for PCI and PMC Cards Document No. DDOC0076-000-AN F-T-MR-S2PCIPMC-A-0-AN...
  • Page 3 Curtiss-Wright Controls, Inc. reserves the right to make changes without notice. Curtiss-Wright Controls, Inc. makes no warranty of any kind with regard to this printed material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
  • Page 4 This product is intended for use in industrial, laboratory, or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments. As a component part of another system, this information technology product has no direct function and is therefore not subject to applicable European Union directives for Information Technology equipment.

  • Page 5: Table Of Contents

    TABLE OF CONTENTS 1. INTRODUCTION ........................1-1 1.1 How to Use This Manual ...................1-1 1.1.1 Purpose .....................1-1 1.1.2 Scope ......................1-1 1.1.3 Style Conventions ..................1-2 1.2 Related Information ....................1-2 1.3 Quality Assurance ......................1-3 1.4 Technical Support ......................1-4 1.5 Ordering Process ......................1-4 2. PRODUCT OVERVIEW ......................2-1 2.1 Overview ........................2-1 2.2 SL240 Features ......................2-4 2.2.1 SFF Media Options ...................2-5...
  • Page 6 4.5.1 Flow Control .....................4-4 4.5.2 Loop Enable .....................4-4 4.5.3 CRC Generation/Checking ...............4-5 4.5.4 Stop on Link Error or /SYNC ..............4-5 4.5.5 Receive FIFO Threshold Interrupt ............4-5 5. APPENDIX A - SPECIFICATIONS ..................5-1 5.1 Specifications ......................5-1 5.1.1 33 MHz PCI Specifications ..............5-1 5.1.2 33 MHz PMC Specifications ..............5-2 5.1.3 66 MHz PCI Specifications ..............5-3 5.1.4 66 MHz PMC Specifications ..............5-3...
  • Page 7 8.2.9 66 MHz SL240 PCI Ordering Information ..........8-2 8.2.10 SL240 FPDP Ordering Information ............8-2 8.2.11 Short Wavelength: Multimode Fiber-Optic Cables ........8-3 8.2.12 Long Wavelength: Single-mode Fiber-Optic Cables ......8-4 8.2.13 HSSDC2 Copper Media Interface: 1.0625 Gbps ........8-5 8.2.14 HSSDC2 Copper Media Interface: 2.5 Gbps ..........8-5 9.
  • Page 8 Copyright 2017 FibreXtreme Hardware Reference...

  • Page 9: Introduction

    This manual introduces the FibreXtreme SL100/SL240 family of products, and provides guidance through the process of unpacking, setting up, and programming the cards. NOTE: Both the FibreXtreme SL100 and SL240 hardware are referred to throughout this manual as SL240. The software that supports both the SL100 and SL240 hardware is referred to as SL240, including the driver and API.

  • Page 10: Style Conventions

    IEC 825-1984 Radiation Safety of Laser Products, Equipment Classification, Requirements, and User’s Guide, 2 parts, 1993.  LinkXchange GLX4000 Physical Layer Switch User Reference Manual (Doc. No. F-T-MR-L5XL144), Curtiss-Wright Controls, Inc.  PCI Local Bus Specification, Revision 2.1, June 1, 1995; PCI Special Interest Group.

  • Page 11: Quality Assurance

    INTRODUCTION 1.3 Quality Assurance Curtiss-Wright Controls’ policy is to provide our customers with the highest quality products and services. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery. Our quality commitment begins with product concept, and continues after receipt of the purchased product.

  • Page 12: Technical Support

    World Wide Web address: www. cwcdefense.com 1.5 Ordering Process To learn more about Curtiss-Wright Controls, Inc. products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time.

  • Page 13: Product Overview

    2.1 Overview The FibreXtreme SL240 cards provide fast, low latency point-to-point or broadcast connections between sensors and processing devices. Curtiss-Wright Controls’ SL240 family of products includes PCI, PCI Mezzanine (PMC), and Front Panel Data Port (FPDP) solutions. The FPDP versions are in two categories—a 6U VME- or PCI-based solution with standard FPDP connectors, and a rehostable Common Mezzanine Card (CMC).

  • Page 14: Figure 2-2 Sl240 Pmc 66 Mhz Card

    PRODUCT OVERVIEW Figure 2-2 SL240 PMC 66 MHz Card Figure 2-3 SL240 PMC Rugged Conduction-Cooled Card (CCPMC) Copyright 2017 FibreXtreme Hardware Reference...

  • Page 15: Figure 2-4 Sl240 Pci 33 Mhz Card

    PRODUCT OVERVIEW Figure 2-4 SL240 PCI 33 MHz Card Figure 2-5 SL100 PMC 5 Volt 33 MHz Rugged Card Copyright 2017 FibreXtreme Hardware Reference...

  • Page 16: Sl240 Features

    PRODUCT OVERVIEW Figure 2-6 SL240 PMC 33 MHz Card 2.2 SL240 Features SL240 provides reliable point-to-point or broadcast interconnects between systems, with minimal overhead and very low latency. The protocol involved for this transport is based on Fibre Channel, though it is not Fibre Channel compliant. The major SL240 features are listed below: ...

  • Page 17: Sff Media Options

    (1550 nm), a long wavelength laser (1300 nm), and HSSDC2 copper. All cards use a Duplex LC style connector or HSSDC2 receptacle, available from most major cable manufacturers. Contact Curtiss-Wright Controls for the latest SFP options available.

  • Page 18: Applications

     Automatic fan speed control based on enclosure temperature.  Fan tachometer monitor. For detailed information regarding the GLX4000 features and operation, contact Curtiss-Wright Controls, Inc. and request a copy of the GLX4000 Physical Layer Switch Hardware Reference Manual or visit our web site. Copyright 2017...

  • Page 19: Typical Digital Signal Processing (Dsp) Imaging System

    PRODUCT OVERVIEW 2.4.2 Typical Digital Signal Processing (DSP) Imaging System With the support for 1.0625 Gbps or 2.5 Gbps link transmission rates between interconnected subsystems, SL240 is ideal for use in many of today’s high-throughput data transfer applications. Figure 2-8 8 shows one example. This figure shows the SL100’s usable data throughput rate.

  • Page 20: Topologies

    2.5.1 Typical Topologies There are four typical topologies for the SL240 card. These topologies should cover most customer applications, though if another topology is desired contact Curtiss-Wright Controls, Inc. Technical Support to see if it is possible. The topologies are: ...

  • Page 21: Chained

    PRODUCT OVERVIEW SL240 SL240 Card Card Figure 2-10 Point-to-Point Topology 2.5.3 Chained This topology is a single transmitter on the end of a long string of receivers. No flow control is available in this topology, and the distance between the nodes is limited only by the transceivers used (10 km typical, 26 km maximum).

  • Page 22: Single Master Ring

    FIFO, it should be switched out to avoid bringing down the loop. A switch suitable for this purpose is the LinkXchange GLX4000 Physical Layer Switch, available from Curtiss-Wright Controls, Inc. Software controls mastership switching of the ring. There are rules associated with master switching listed in the “Programming Interface” section. The flow control used in this case is similar to a multi-drop FPDP bus, where any receiver can back the transmitter off.

  • Page 23: Multiple Master Ring

    PRODUCT OVERVIEW 2.5.5 Multiple Master Ring This is another form of ring topology, where there are multiple masters on the ring, and these masters have to receive data as well as transmit data to the next master. In the most complex case, each node is a master, which means that it receives data from the previous master and sends data to the next master.

  • Page 24: Status Leds

    PRODUCT OVERVIEW 2.6 Status LEDs 2.6.1 LED Description for SL100 and SL240 33MHz Cards Four status LEDs are visible form the front panel of the SL240 board. The position of the LEDs is shown in Figure 2-144 for PMC cards and Figure 2-155 for the PCI cards. Link Select (LS) This LED is reserved for future use.

  • Page 25: Led Description For Sl240 66Mhz Cards

    PRODUCT OVERVIEW 2.6.2 LED Description for SL240 66MHz Cards Four status LEDs are visible form the front panel of the SL240 board. The position of the LEDs is shown in Figure 2-166 for PMC cards and Figure 2-177 for the PCI cards. Link Up (LU) The Link Up LED turns on when receiving a valid SL240 signal.

  • Page 27: Installation

    3.3 Inspect the Cards The SL240 card consists of a single card with a built-in link interface. If the card was damaged in shipping, notify Curtiss-Wright Controls, Inc. or your supplier immediately. 3.4 Configure the SL240 Card 3.4.1 Installing SFP Modules The physical media interface of the SL240 design uses SFP transceiver modules.

  • Page 28: Install The Cards

    INSTALLATION To insert an SFP module, hold the module with the PCB cutout facing downward toward the Sl240 card and slide it into the receptacle cage on the card. There will be a small click as the module latches into place. The SFP module is designed to only fit into the receptacle cage a certain way.

  • Page 29: Sl240 Pmc Card

    INSTALLATION 3.5.2 SL240 PMC Card To install the SL240 PMC card into an available carrier slot, insert the faceplate into the carrier front panel cutout until it butts up against the mating connector as shown in Figure 3-2, steps 1 and 2. Then firmly push the connectors together. Install the four mounting screws through the host PCB to fasten the SL240 PMC card in place, as shown in step 3.

  • Page 30: Connect The Cables

    INSTALLATION 3.6 Connect the Cables 3.6.1 Transmission Media For short wavelength laser modules, either a 50 µm or 62.5 µm core diameter cable should be used. For distances up to 300 meters 62.5 µm can be used. 50 µm cable allows distances up to 500 meters.

  • Page 31: Hssdc2 Copper Cables

    INSTALLATION 3.6.3 HSSDC2 Copper Cables The copper media interface on the SL240 cards support shielded cable, terminated with HSSDC2 style connectors, shown in Figure 3-5. Figure 3-6 displays the HSSDC2 SFP receptacle used on the SL240 cards. This figure indicates the HSSDC2 contact pin locations and Table 3-1 contains the pin assignments.

  • Page 32: Troubleshooting

    INSTALLATION 3.7 Troubleshooting If the system does not boot correctly, power down the machine, reseat the card, double- check cable connections, and turn the system back on. If problems persist, contact Curtiss- Wright Controls, Inc. Technical Support at (800) 252-5601 or DTN_support@ curtisswright.com for assistance.

  • Page 33: Operation

    4. OPERATION 4.1 Overview SL100/SL240 cards move data with very low latency between a host interface and a 1.0625 Gbps or a 2.5 Gbps link, respectively. The host interfaces available are an FPDP- like proprietary interface and a PCI interface. The advantage of the FPDP-like interface is that it requires very simplistic hardware to interface.

  • Page 34: Transmit Operation

    4.2.3 Loop Operation In the Loop Operation discussion below, SL100/SL240 is used generically to refer to any Curtiss-Wright Controls, Inc. SL100/SL240 card (PCI, PMC, or CMC). Anything that applies to only a specific SL100/SL240 product will be noted as such.
  • Page 35 FPDP transmitter, depending of the usage of /NRDY used by the respective FPDP transmit master. Curtiss-Wright Controls’ SL100/SL240 CMC cards, when functioning as a FPDP transmit master, will stop the transmission of FPDP data when /NRDY is asserted by the FPDP receiver.

  • Page 36: Data Synchronization

    In some rare cases, flow control is not desirable. In these cases, very careful system planning is required, which should be confirmed with Curtiss-Wright Controls, Inc. prior to architectural finalization. One possible exception is for applications that cannot use a duplex fiber-optic link, which means status information (link up and state of flow control) is not available from the remote node.

  • Page 37: Crc Generation/Checking

    OPERATION 4.5.3 CRC Generation/Checking The CRC Generation/Checking option allows the SL240 card to detect data transmission errors. The card is not capable of correcting the errors. Error correction is left to application level design. A single bit controls both generation and checking. CRC should be used in almost all applications.
  • Page 38 OPERATION This page intentionally left blank Copyright 2017 FibreXtreme Hardware Reference...
  • Page 39 5. APPENDIX A - SPECIFICATIONS TABLE OF CONTENTS 5.1 Specifications ............................5-1 5.1.1 33 MHz PCI Specifications ........................5-1 5.1.2 33 MHz PMC Specifications ........................ 5-2 5.1.3 66 MHz PCI Specifications ........................5-3 5.1.4 66 MHz PMC Specifications ........................ 5-3 5.1.5 66 MHz CCPMC Specifications (Conduction-Cooled Rugged Level 2) ..........

  • Page 41: Appendix A - Specifications

    SPECIFICATIONS 5.1 Specifications NOTE: “Peak” current specifications are based on measurements taken while the card was transmitting and receiving large buffers of data. “Average” current specifications are based on measurements taken while the card was powered on but not transmitting or receiving any data.

  • Page 42: 33 Mhz Pmc Specifications

    SPECIFICATIONS 5.1.2 33 MHz PMC Specifications Physical Dimensions: ......74.0 mm x 149.0 mm (2.913 inches x 5.866 inches) Weight:.......... 0.25 lbs Operating Voltage: ....... 4.75 V to 5.25 V Power Dissipation: SL100 ..........5.1 W Peak, 3.1 W Average SL240 ..........

  • Page 43: 66 Mhz Pci Specifications

    SPECIFICATIONS 5.1.3 66 MHz PCI Specifications Physical Dimensions: ......174.6 mm x 106.7 mm (6.87 inches x 4.20 inches) Weight:.......... 0.25 lbs Operating Voltage: ....... 5 V ±5% Power Dissipation: SL100 ..........5.1W Peak, 3.1W Average SL240 ..........7.4W Peak, 4.3W Average Electrical Requirements: SL100 ..........

  • Page 44: 66 Mhz Ccpmc Specifications (Conduction-Cooled Rugged Level 2)

    SPECIFICATIONS 5.1.5 66 MHz CCPMC Specifications (Conduction-Cooled Rugged Level 2) Physical Dimensions: ......74.0 mm x 149.0 mm (2.913 inches x 5.866 inches) Weight:.......... 0.25 lbs Operating Voltage: ....... 3.3V ±5% Power Dissipation: SL100 ........5.3W Peak, at 3.3V SL240 ........

  • Page 45: Ruggedized Pmc Environmental Specifications

    SPECIFICATIONS 5.2 Ruggedized PMC Environmental Specifications The SL100/SL240 PMC products are offered at ruggedization level 2. The specifications for Rugged Level 2 are defined in the following section. Current SL100/SL240 PMC standard and ruggedized products are listed in Appendix D. 5.2.1 Rugged Level 2 Temperature Range: Operating ........

  • Page 46: Media Interface Specifications

    SPECIFICATIONS 5.3 Media Interface Specifications 5.3.1 SL100 Fibre-Optic Media Interface Specifications Connector: ..........Duplex LC 850 nm: Media ..........50 µm or 62.5 µm multimode fiber Fibre Channel Formats: ....100-M5-SN-I (1 Gbps, 50 µm fiber) 100-M6-SN-I (1 Gbps, 62.5 µm fiber) Maximum Fiber Length: ....

  • Page 47: Sl240 Fibre-Optic Media Interface Specifications

    SPECIFICATIONS 5.3.2 SL240 Fibre-Optic Media Interface Specifications Connector: ..........Duplex LC 850 nm: Media ..........50 µm or 62.5 µm multimode fiber Maximum Fiber Length: ....250 m with 50 µm fiber 125 m with 62.5 µm fiber Transmit Wavelength: ....830 to 860 nm Transmit Power: ......
  • Page 48 SPECIFICATIONS Copyright 2017 FibreXtreme Hardware Reference...

  • Page 49: Appendix B - Register Set

    6. APPENDIX B - REGISTER SET TABLE OF CONTENTS 6.1 Overview ........................6-1 6.2 Accessible resources....................6-1 6.3 PCI Configuration registers ..................6-1 6.4 Runtime Register set ....................6-1 6.4.1 Bit Definitions ..................6-1 6.4.2 Interrupt CSR (INT_CSR) – Offset 0x00 ..........6-3 6.4.3 Board CSR (BRD_CSR) –...

  • Page 51: Overview

    REGISTERS 6.1 Overview NOTE: The FibreXtreme SL100 and SL240 PCI and PMC Cards will be referred to throughout this appendix as PCI. Anything that is exclusive to the PCI or PMC Cards will be described as such. The PCI SL240 card is very easy to program. With minimal programming, the PCI SL240 card can transfer data between PCI hosts.
  • Page 52 REGISTERS Table 6-1 SL240 Register Layout REGISTER LAYOUT 0x00 Board CSR Interrupt CSR 0x08 Link Status Link Control 0x10 Receive FIFO Threshold FPDP Flags 0x18 Reserved Laser Transmitter Control 0x20 Reserved Queue Address 0 0x28 Reserved Queue Control 0 0x30 Transaction Length 0 Transaction CSR 0 0x38...

  • Page 53: Interrupt Csr (Int_Csr) - Offset 0X00

    REGISTERS 6.4.2 Interrupt CSR (INT_CSR) – Offset 0x00 Field Description Access Reset Value Transaction Channel 0 Interrupt Active – A ‘1’ indicates R/WOC active, a ‘0’ indicates not active. Write ‘1’ to clear. Transaction Channel 1 Interrupt Active – A ‘1’ indicates R/WOC active, a ‘0’...

  • Page 54: Board Csr (Brd_Csr) - Offset 0X04

    REGISTERS 6.4.3 Board CSR (BRD_CSR) – Offset 0x04 Field Description Access Reset Value Little Endian – Set to ‘1’ for unswapped control registers. Setting to ‘0’ has no effect. Reset – Write ‘1’ to reset the board. Writing ‘0’ has no effect.

  • Page 55: Link Control (Link_Ctl) - Offset 0X08

    Curtiss-Wright Controls, Inc. prior to architectural finalization. One possible exception is for applications that cannot utilize a duplex fiber optic link, which means status information (link up and state of flow control) is not available from the remote node.
  • Page 56 REGISTERS Field Description Access Reset Value SYNC as D0 – If ‘1’ then bit 0 of the data stream is used as /SYNC in the outgoing and incoming data stream. If ‘0’, bit 0 is not used as /SYNC. Reserved None Disable Receiver –...
  • Page 57 REGISTERS Field Description Access Reset Value chain should have this bit set to '0.' Do not set this bit to '1' on any device in a point-to-point topology (i.e. two cards) because throughput will decrease by a factor related to frame size. This bit was introduced in the revision 0x1C.13 firmware.

  • Page 58: Link Status (Link_Stat) - Offset 0X0C

    REGISTERS 6.4.5 Link Status (LINK_STAT) – Offset 0x0C Field Description Access Reset Value 8B10B Errors – 8-bit counter counting the current 7 to 0 0x00 number of 8B10B decoding errors discovered. Cleared through ‘Reset SR’ in LINK_CTL Link Down – A ‘1’ indicates the link has gone down at some point since the last ‘Reset SR’.

  • Page 59: Fpdp Flags (Fpdp_Flgs) - Offset 0X10

    REGISTERS 6.4.6 FPDP Flags (FPDP_FLGS) – Offset 0x10 Field Description Access Reset Value Send SYNC – Write ‘1’ to send SYNC without DVALID. Writing ‘0’ has no effect. PIO1 Out – State of the PIO1 line sent across the link. PIO2 Out –...

  • Page 60: Receive Fifo Threshold - Offset 0X14

    REGISTERS 6.4.7 Receive FIFO Threshold – Offset 0x14 NOTE: The lower 20 bits of this register, indicating the number of 32-bit words, is limited to showing a 4 MB value. This count value will decrement and roll over several times when reading data out of a full 128 MB receive FIFO. i.e. word count will indicate a decrementing count from 4 MB down to 0.

  • Page 61: Transaction Channel 0 (Send Channel)

    REGISTERS 6.4.9 Transaction Channel 0 (Send Channel) Send Queue Address (QADDR0) – Offset 0x20 Field Description Access Reset Value Reserved – Write as ‘0’ 3 to 0 None 31 to 4 Bits 31 through 4 of PCI address for the transaction queue.
  • Page 62 REGISTERS Send Transaction CSR (TNS_CSR0) – Offset 0x30 Field Description Access Reset Value Interrupt Enable – Set to ‘1’ to enable an interrupt on this transaction. Set to ‘0’ for normal operation. Skip entry – skips to the next entry when this bit is set. Set to ‘1’...
  • Page 63 REGISTERS Send Chain Length/Flags (CLENFLGS0) – Offset 0x48 Field Description Access Reset Value 23 to 0 Length of buffer in 32-bit words. End Chain – Write ‘1’ to say this is the last chain entry. Write ‘0’ if it is not. Reserved.

  • Page 64: Transaction Channel 1 (Receive Channel)

    REGISTERS 6.4.10 Transaction Channel 1 (Receive Channel) Receive Queue Address (QADDR1) – Offset 0x50 Field Description Access Reset Value Reserved – Write as ‘0’ 3 to 0 None 31 to 4 Bits 31 through 4 of PCI address for the transaction queue.
  • Page 65 REGISTERS Receive Transaction CSR (TNS_CSR1) – Offset 0x60 Field Description Access Reset Value Interrupt Enable – Set to ‘1’ to enable an interrupt on this transaction. Set to ‘0’ for normal operation. Skip entry – Skips to the next entry when this bit is set. Set to ‘1’...
  • Page 66 REGISTERS Receive Chain Length/Flags (CLENFLGS1) – Offset 0x78 Field Description Access Reset Value 23 to 0 Length of buffer in 32-bit words. End Chain – Write ‘1’ to say this is the last chain entry. Write ‘0’ if it is not. Reserved.
  • Page 67 7. APPENDIX C - SL100/SL240 PROTOCOL TABLE OF CONTENTS 7.1 Overview ........................7-1 7.2 Ordered Sets Used .....................7-1 7.3 Frames ........................7-3 7.3.1 Link Bandwidth ..................7-4 7.3.2 FPDP Signal Sample Rate ................7-4 7.4 Data Transmission and Flow Control ................7-5 FIGURES Figure 7-1 VITA 17.1 Framing Protocol ..................7-3 TABLES Table 7-1 Ordered Set Mapping .....................7-2 Table 7-2 Maximum Sustained Throughput ..................7-4...

  • Page 69: Appendix C - Sl100/Sl240 Protocol

    SL100/SL240 PROTOCOL 7.1 Overview NOTE: The FibreXtreme SL100 and SL240 PCI and PMC Cards will be referred to throughout this appendix as PCI. Anything that is exclusive to the PCI or PMC Cards will be described as such. The SL100/SL240 Serial FPDP protocol (also known as VITA 17.1) is designed to provide near optimal throughput while maintaining low overhead.
  • Page 70 SL100/SL240 PROTOCOL Table 7-1 Ordered Set Mapping Fibre Channel VITA 17.1 Description Ordered Set Ordered Set Start of Frame: SOFc1 PIO1 = 0, PIO2 = 0, DIR = 0 Start of Frame: SOFi1 PIO1 = 0, PIO2 = 0, DIR = 1 Start of Frame: SOFn1 PIO1 = 0, PIO2 = 1, DIR = 0...

  • Page 71: Frames

    SL100/SL240 PROTOCOL 7.3 Frames There are four basic frame types defined in VITA 17.1 – an IDLE frame, data frame, a SYNC without data frame, and a SYNC with data frame. The data is divided into frames so the FPDP signals are sampled at some minimum interval, and so the receiver is guaranteed to see IDLEs to maintain synchronization.

  • Page 72: Link Bandwidth

    SL100/SL240 PROTOCOL 7.3.1 Link Bandwidth With CRC disabled and the Copy Mode Master bit clear (‘0’), there is a five-word overhead for every frame transmitted. Since frames can contain up to 512 words of data, this results in an efficiency of 99.03%. With CRC enabled and the Copy Master bit clear, there is a six-word overhead for every frame transmitted.

  • Page 73: Data Transmission And Flow Control

    GO—if it is STOP, then the data waits in the Transmit FIFO until the signal changes. Curtiss-Wright Controls’ SL100/SL240 boards use the same protocol when transmitting from either end to allow the link to operate bi-directionally.
  • Page 75 8. APPENDIX D - ORDERING INFORMATION TABLE OF CONTENTS 8.1 Overview ........................8-1 8.2 Ordering Information ....................8-1 8.2.1 33 MHz SL100 PMC Ordering Information ..........8-1 8.2.2 33 MHz SL100 PCI Ordering Information ..........8-1 8.2.3 66 MHz SL100 PMC Ordering Information ..........8-1 8.2.4 66 MHz SL100 PCI Ordering Information ..........
  • Page 77 TABLES Table 3-1 HSSDC2 Receptacle Pin Assignments for SL100 ............3-5 Table 3-2 HSSDC2 Receptacle Pin Assignments for SL240 ............3-5 Table 6-1 SL240 Register Layout ....................6-2 Table 7-1 Ordered Set Mapping ....................7-2 Table 7-2 Maximum Sustained Throughput .................. 7-4 Table 7-3 Sampling Frequencies ....................

  • Page 79: Appendix D - Ordering Information

    ORDERING INFORMATION 8.1 Overview This appendix contains the order number for all Curtiss-Wright Controls, Inc. products mentioned in this manual. For an up to date list, or for inquiries about these products, contact Curtiss-Wright Controls, Inc. Defense Solutions Center Sales.

  • Page 80: Sl100 Fpdp Ordering Information

    ORDERING INFORMATION 8.2.5 SL100 FPDP Ordering Information Table 8-5 66 MHz SL100 FPDP Order Number Description FHK4-FM4MWB04-00 SL100 CMC, 850 nm laser 8.2.6 33 MHz SL240 PMC Ordering Information Table 8-6 33 MHz SL240 PMC Order Number Description FHK7-PM6MWB04-00 SL240 PMC, 850 nm SFP laser, 5 V PCI signaling voltage 8.2.7 33 MHz SL240 PCI Ordering Information Table 8-7 33 MHz SL240 PCI Order Number...

  • Page 81: Short Wavelength: Multimode Fiber-Optic Cables

    ORDERING INFORMATION 8.2.11 Short Wavelength: Multimode Fiber-Optic Cables The following table lists the order numbers for the simplex and duplex, 50/125 m multimode fiber-optic cables, for use with the short wavelength laser media interface. Table 8-11 LC to LC Simplex Duplex Length Cable End 1...

  • Page 82: Long Wavelength: Single-Mode Fiber-Optic Cables

    ORDERING INFORMATION 8.2.12 Long Wavelength: Single-mode Fiber-Optic Cables The following table lists the order numbers for the simplex and duplex, 9/125 m single- mode fiber-optic cables, for use with the long wavelength laser media interface. Table 8-14 LC to LC Simplex Duplex Length...

  • Page 83: Hssdc2 Copper Media Interface: 1.0625 Gbps

    ORDERING INFORMATION 8.2.13 HSSDC2 Copper Media Interface: 1.0625 Gbps Shielded 150-Ohm Shielded Quad copper cable with HSSDC2 (Fibre Channel) connectors, for use with the HSSDC2 copper media interface. Table 8-16 Shielded 150-Ohm Quad Copper Cable with HSSDC2 (Fibre Channel) Connectors Order Number Description FHAC-Q2H11000-00...
  • Page 85 9. APPENDIX E - FPDP PRIMER TABLE OF CONTENTS 9.1 FPDP Overview ........................9-1 9.2 Terminology ........................9-3 9.3 Parallel FPDP Theory of Operation..................9-3 9.3.1 Clock Signals ....................9-3 9.3.2 Data Framing..................... 9-4 9.4 Serial FPDP Theory of Operation ..................9-5 9.5 Parallel FPDP Signal Timing .....................

  • Page 87: Appendix E - Fpdp Primer

    FPDP PRIMER 9.1 FPDP Overview This section provides a brief discussion of Front Panel Data Port (FPDP). For more information about FPDP, refer to Front Panel Data Port Specifications, ANSI/VITA 17- 1998 or go to the VITA website at: www.vita.com/vso/. The SL100/SL240 cards implement a serial version of FPDP on their link interface, which is standard VITA 17.1.

  • Page 88: Figure 9-1 Example Configuration With Multiple Vme Fpdp Cards Connected

    FPDP PRIMER FPDP-TM FPDP-R FPDP-R FPDP-R FPDP-R FPDP-RM Figure 9-1 Example Configuration With Multiple VME FPDP Cards Connected Several advantages of an FPDP interface include:  Simple hardware is required to interface to FPDP.  FPDP does not interfere with the normal bus operations—VME or PCI traffic can continue without data transfers wasting bus bandwidth.

  • Page 89: Terminology

    FPDP PRIMER Some additional advantages of parallel FPDP are:  Low cost, 32-bit parallel interface provided through a ribbon cable.  160 MBps sustained data rate. Some additional advantages of Serial FPDP are:  Noise immune fiber-optic interface.  Significantly increased transmission distance (10 km). ...

  • Page 90: Data Framing

    FPDP PRIMER 9.3.2 Data Framing The FPDP specification does not allow for the transmission of address information. However, many systems have data coming from several cards or channels. The way to identify data from each channel is through framing. A synchronization pulse signal, /SYNC, was defined for framing purposes.

  • Page 91: Serial Fpdp Theory Of Operation

    FPDP PRIMER When fixed or dynamic size repeating frame data is transmitted onto the FPDP bus, the FPDP-TM must assert a /SYNC pulse while /DVALID is already asserted. The /SYNC pulse must be asserted at the same time as the last data item of every frame.

  • Page 92: Parallel Fpdp Signal Timing

    FPDP PRIMER 9.5 Parallel FPDP Signal Timing Figure 9-2 shows the timing for several FPDP interface signals. This figure is accurate for all four data framing types. See section 9.3.2 for a discussion of framing. The Data Valid signal, /DVALID, is asserted by the FPDP-TM when valid data is transmitted onto the FPDP bus but not before at least 16 STROBE periods have occurred.

  • Page 93: Figure 9-2 Parallel Fpdp Interface Timing Diagram

    FPDP PRIMER Figure 9-2 Parallel FPDP Interface Timing Diagram Copyright 2017 FibreXtreme Hardware Reference...

  • Page 94: Figure 9-3 Fpdp Timing Diagrams Showing The Use Of Framing

    FPDP PRIMER Figure 9-3 FPDP Timing Diagrams Showing the Use of Framing Copyright 2017 FibreXtreme Hardware Reference...
  • Page 95 FPDP PRIMER The timing parameters from Figures E-2 and E-3 are detailed in Tables E-1 and E-2. These timing specifications are taken from Front Panel Data Port Specifications, ANSI/VITA 17. Table 9-1 Parallel FPDP Timing Specifications Parameter Description At Transmitter At Receiver FPDP End of Cable...

  • Page 97: Index

    10. INDEX 1.0625 Gbps, 7-1 point-to-point, 2-1, 2-4 8B/10B connector encoding, 7-1 duplex LC, 2-5, 3-4, 5-6, 5-7 8B/10B decoding, 4-3 HSSDC2, 3-5, 8-5 8B/10B encoding, 2-4 simplex LC, 3-4 8B10B Connector decoding errors, 6-10 HSSDC2, 5-7 active low, 7-1 connectors airflow, 5-5 fiber-optic, 3-4...
  • Page 98 INDEX stop conditions, 4-6 IDLE, 7-4 DMA engine, 4-6 SYNC with data, 7-4 DMA transaction, 4-1 SYNC without data, 7-4 DMA transaction, 4-2 types, 7-4 electrical isolation, 2-7 frame size electrical requirements, 5-1, 5-2, 5-3, 5-4 maximum, 4-6 electrostatic discharge, 3-1 frame size, 4-2 EMI performance, 3-2 framing-state machine, 4-2...
  • Page 99 INDEX transmit control, 4-2 theory, 4-1 loop, 3-4 transmit, 4-2 configuration, 4-3 Order, 8-5 master, 4-3 order numbers mode, 6-7, 6-8 multimode FO, 8-3 operation, 2-4, 4-3, 4-4, 4-6 singlemode fiber optic, 8-4 retransmission, 4-3 ordered set, 7-4 loop master, 2-11, 4-2 ordered sets, 4-3, 4-4, 6-8, 7-1, 7-2, 7-5 loop-enable option, 4-5 parallel port...
  • Page 100 INDEX set, 2-4 SYNC without DVALID, 6-8, 6-18 status, 6-1 timing, 9-3 threshold, 6-1 signaling voltage register set, 4-3, 4-4 3.3 V PCI, 8-1, 8-2 ribbon cable, 9-1, 9-3 5 V PCI, 8-1, 8-2 ruggedization levels, 5-5 single-board computer, 2-1 ruggedized, 2-4 specifications Ruggedized, 5-5...
  • Page 101 INDEX transaction queue, 6-14, 6-17 transmit wavelength, 5-6, 5-7 transactions unpack, 3-1 64-bit, 6-4 vibration, 5-5 transfer rate video transmission applications, 2-9 link, 7-1 virtual FPDP bus, 4-2 maximum, 9-3 VITA 17.1, 4-3, 4-4, 7-1, 7-2, 7-4, 9-1 transmission distance, 9-3 VME chassis, 9-2 transmission rates weight, 5-1, 5-2, 5-3, 5-4...

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