Page 1  SL100/SL240 Hardware Reference for Carrier and Rehostable CMC FPDP Legacy Cards F-T-MR-S3FPDP##-A-0-B1...
Page 3 Curtiss-Wright Controls, Inc reserves the right to make changes without notice. Curtiss-Wright Controls, Inc. makes no warranty of any kind with regard to this printed material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
Page 4 This product is intended for use in industrial, laboratory or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.
Page 5: Table Of Contents
TABLE OF CONTENTS 1. INTRODUCTION ............................1-1 1.1 How to Use This Manual ......................1-1 1.1.1 Purpose ........................1-1 1.1.2 Scope ........................1-1 1.1.3 Style Conventions ....................1-2 1.2 Related Information ........................1-2 1.3 Quality Assurance ........................1-3 1.4 Technical Support ........................1-4 1.5 Ordering Process ........................
Page 6 TABLE OF CONTENTS 4.4.6 Receive FIFO Threshold Interrupt ................. 4-5 5. APPENDIX A - SPECIFICATIONS ......................5-1 5.1 Overview ..........................5-1 5.2 Rehostable CMC FPDP Card Specifications ................5-1 5.3 PCI FibreXtreme Carrier Card Specifications ................5-2 5.4 FPDP Connector Pin Assignments ................... 5-3 5.5 RS-232 Pin-out on PCI FibreXtreme Carrier ................
Page 7 TABLE OF CONTENTS 9.3.1 Short Wavelength: Multimode Fiber-Optic Cable ..........9-2 9.3.2 Long Wavelength: Singlemode Fiber-Optic Cable ..........9-3 9.3.3 HSSDC2 Copper Media Interface: 1.0625 Gbps ........... 9-3 9.3.4 HSSDC2 Copper Media Interface: 2.5 Gbps ............9-4 10. APPENDIX F - FPDP PRIMER ......................10-1 10.1 FPDP Overview ........................
Page 8 TABLE OF CONTENTS Figure 3-2 FPDP Connectors ......................... 3-3 Figure 3-3 Fiber-optic Simplex LC Connector ....................3-4 Figure 3-4 Fiber-optic Duplex LC Connector ....................3-4 Figure 3-5 HSSDC2 Copper Connector ......................3-5 Figure 3-6 HSSDC2 Receptacle Contact Pin Locations ................. 3-5 Figure 5-1 RJ-45 Female to DB-9 Female Adapter ..................
Page 9: Introduction
1.1 How to Use This Manual 1.1.1 Purpose This manual describes the FibreXtreme SL100 SL240 CMC FPDP Legacy card, and guides you through the process of unpacking, setting up, and using the card. NOTE: Both the FibreXtreme SL100 and SL240 hardware are referred to throughout this manual as SL240.
Page 10: Style Conventions
IEC 825-1984 Radiation Safety of Laser Products, Equipment Classification, Requirements, and User’s Guide, 2 parts, 1993. • FibreXtreme SL100/SL240 Hardware Reference Manual for PCI, PMC, and CPCI Cards, (Doc. No. F-T-MR-S2PCIPMC), Curtiss-Wright Controls, Inc. • LinkXchange LX1500e Physical Layer Switch Hardware Reference Manual, (Doc.
Page 11: Quality Assurance
INTRODUCTION 1.3 Quality Assurance Curtiss-Wright Controls policy is to provide our customers with the highest quality products and services. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery. Our quality commitment begins with product concept, and continues after receipt of the purchased product.
Page 12: Technical Support
World Wide Web address: www.cwcdefense.com 1.5 Ordering Process To learn more about Curtiss-Wright Controls’ products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time. •...
Page 13: Product Overview
2. PRODUCT OVERVIEW 2.1 Overview The FibreXtreme SL240 cards provide fast, low latency point-to-point or broadcast connections between sensors and processing devices. The FPDP versions include a PCI- based solution with standard FPDP connectors and a rehostable Common Mezzanine Card (CMC). The CMC card provides this interface through a simple unidirectional parallel port.
Page 14: Media Options
(< 300 m). HSSDC interconnections are recommended for very short distances of 30 meters or less. All cards use a Duplex LC style connector or HSSDC2 receptacle, available from most major cable manufacturers. For details concerning this connector, contact Curtiss-Wright Controls, Inc. Technical Support. 2.3 SL240 Cards This section contains photographs of the SL240 CMC and FPDP PCI Carrier cards.
Page 15: Fpdp Card Features
PRODUCT OVERVIEW Figure 2-2 PCI FibreXtreme Carrier Card 2.3.1 FPDP Card Features The major features of the various FPDP cards are listed below. See Table 2-1 for a summary of all FPDP card features. NOTE: The FPDP bus speeds are derived from the reference clock (53.125 MHz or 125 MHz) divided by 2, 3, 4, or 6.
Page 16: Applications
• Automatic fan speed control based on enclosure temperature. • Fan tachometer monitor. For detailed information regarding the GLX4000 features and operation, contact Curtiss-Wright Controls, Inc. and request a copy of the GLX4000 Physical Layer Switch Hardware Reference Manual or visit our web site. Copyright 2012...
Page 17: Typical Digital Signal Processing (Dsp) Imaging System
PRODUCT OVERVIEW 2.4.2 Typical Digital Signal Processing (DSP) Imaging System With the support for 1.0625 Gbps or 2.5 Gbps link transmission rates between interconnected subsystems, SL240 is ideal for use in many of today’s high-throughput data transfer applications. One example is shown in Figure 2-3. This figure shows the SL100’s usable data throughput rate.
Page 18: Extending Fpdp
2.5.1 Typical Topologies There are four typical topologies for the SL240 card. These topologies should cover most customer applications, though if another topology is desired contact Curtiss-Wright Controls Technical Support to see if it is possible. The topologies are: •...
Page 19: Chained
PRODUCT OVERVIEW There are many applications for the point-to-point topology—as long as it involves only two nodes, this topology covers it. One advantage that point-to-point has over the other topologies is the ability to do simultaneous bi-directional traffic. SL240X SL240X Card Card Figure 2-5 Point-to-Point Topology...
Page 20: Single Master Ring
Receive FIFO, it should be switched out to avoid bringing down the loop. A Physical Layer Switch suitable for this purpose is the LinkXchange GLX4000, available from Curtiss-Wright Controls, Inc. Software controls mastership switching of the ring. There are rules associated with master switching listed in the “Programming Interface”...
Page 21: Multiple Master Ring
PRODUCT OVERVIEW 2.5.5 Multiple Master Ring This is another form of ring topology, where there are multiple masters on the ring, and these masters have to receive data as well as transmit data to the next master. In the most complex case, each node is a master, which means that it receives data from the previous master and sends data to the next master.
Page 22: Status Leds
PRODUCT OVERVIEW 2.6 Status LEDs 2.6.1 SL240 CMC LEDs Four status LEDs are visible form the front panel of the SL240 board. The position of the LEDs is shown in Figure 2-9 for CMC card. Link Select (LS) This LED is reserved for future use. The on/off condition of this LED is of no consequence.
Page 23: Pci Carrier Card Status Leds
PRODUCT OVERVIEW 2.6.2 PCI Carrier Card Status LEDs The PCI FibreXtreme Carrier card has three LEDs. These LEDs (D1, D2, D3) viewed from the component side of the card are shown in Figure 2-10. MICRO The LED labeled “MICRO” is currently not used and will remain unlit. Receive Interface (RX OK) When the LED labeled “RX OK”...
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Page 25: Installation
FPDP interface. A FibreXtreme SL240 rehostable CMC FPDP card consists of a single card with a built-in link interface. If the card was damaged in shipping, notify Curtiss-Wright Controls or your supplier immediately. Copyright 2012 FibreXtreme HW Reference for FPDP Cards...
Page 26: Install The Card
INSTALLATION 3.4 Install the Card WARNING: Before installing any peripheral component into a computer, ensure the system is powered off. 3.4.1 PCI FibreXtreme Carrier Card Installation To install the PCI FibreXtreme Carrier card, push the card into the mother card, as shown in Figure 3-1, steps 1 and 2, until it is firmly seated.
Page 27: Configure The Cards
Figure 3-2 FPDP Connectors NOTE: does not provide the FPDP cables. Please use the Curtiss-Wright Controls, Inc. Robinson-Nugent connector (part number: P50E-080S-TG) to make your own cable set or contact the appropriate cable vendor to acquire the cable set you desire.
Page 28: Fiber-Optic Cables
INSTALLATION 3.6.2 Fiber-optic Cables The two factors to consider when connecting the cables are the topology and the transmission media used. There are several different topologies the cards can be connected in, depending on your application. See section 2.5 for more detailed examples of topologies.
Page 29: Copper Cables
INSTALLATION 3.6.3 Copper Cables The copper media interface on the SL100X/SL240 cards support shielded cable, terminated with HSSDC2 style connectors, shown in Figure 3-5. Figure 3-6 displays the HSSDC2 SFP receptacle used on the SL100X/SL240 cards. This figure indicates the HSSDC2 contact pin locations and Table 3-1 contains the pin assignments.
Page 30: Troubleshooting
If the system does not boot correctly, power down the machine, reseat the card, double- check cable connections, and turn the system back on. If problems persist, contact Curtiss-Wright Controls Technical Support at (800) 252-5601 or DTN_support@curtisswright.com for assistance. Please be prepared to supply the following information:...
Page 33: Operation
4. OPERATION 4.1 Overview SL100/SL240 cards move data with very low latency between a host interface and a 1.0625 Gbps or a 2.5 Gbps link, respectively. The host interfaces available is an FPDP- like proprietary interface. The advantage of the FPDP-like interface is that it requires very simplistic hardware to interface.
Page 34: Transmit Operation
4.2.3 Loop Operation In the Loop Operation discussion below, SL100/SL240 is used generically to refer to any Curtiss-Wright Controls SL100/SL240 card. Anything that applies to only a specific SL100/SL240 product will be noted as such. Loop operation with the SL100/SL240 acts like a virtual FPDP bus where one source (the loop master) can transmit to any number of receive nodes.
Page 35: Data Synchronization
NRDY from the link interface may be used to back off the FPDP transmitter, depending of the usage of /NRDY used by the respective FPDP transmit master. Curtiss-Wright Controls’ SL100/SL240 CMC cards, when functioning as a FPDP transmit master, will stop the transmission of FPDP data when /NRDY is asserted by the FPDP receiver.
Page 36: Configuration Options
Some exotic conditions could apply where flow control is not desirable, but they require very careful system planning and should be confirmed with Curtiss-Wright Controls prior to architectural finalization. One possible exception is for applications that cannot use a duplex fiber- optic link, which means status information (link up and state of flow control) is not available from the remote node.
Page 37: Stop On Link Error Or /Sync
OPERATION 4.4.5 Stop on Link Error or /SYNC There are two DMA stop conditions available to the user—stop on link error and stop on /SYNC. The stop on link error stops the DMA engine from removing data from the Receive FIFO when there is a link error, such as the link going down. The stop on /SYNC option allows you to stop data from being received from the Receive FIFO when a /SYNC without /DVALID is received on the output.
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Page 39 5. APPENDIX A - SPECIFICATIONS TABLE OF CONTENTS 5.1 Overview ...........................5-1 5.2 Rehostable CMC FPDP Card Specifications ................5-1 5.3 PCI FibreXtreme Carrier Card Specifications ................5-2 5.4 FPDP Connector Pin Assignments ....................5-3 5.5 RS-232 Pin-out on PCI FibreXtreme Carrier ................5-4 5.6 Media Interface Specifications ....................5-5 5.6.1 SL100 Fiber-Optic Media Interface Specifications ..........5-5 5.6.2 SL240 Fiber-Optic Media Interface Specifications ..........5-5 5.6.3 SL100 HSSDC2 Copper Media Interface ...............5-6...
Page 41: Appendix A - Specifications
SPECIFICATIONS 5.1 Overview This section shows the general card specifications of the FibreXtreme SL100/SL240 PCI and rehostable CMC FPDP cards and FPDP connector pin assignments. NOTE: “Peak” current requirements represent a measured maximum for a typical card. Measurements were taken while the card was transmitting and receiving large buffers of data.
Page 42: Pci Fibrextreme Carrier Card Specifications
SPECIFICATIONS 5.3 PCI FibreXtreme Carrier Card Specifications Physical Dimensions: ........... 174.6 x 106.7 mm Weight: ..............≈ 0.40 lbs Operating Voltage: ..........4.75 V to 5.25 V Electrical Requirements: SL100 ..............+5 VDC, 0.3 Amps SL240 ..............+5 VDC, 0.3 Amps Operating Temperature Range: ......
Page 43: Fpdp Connector Pin Assignments
SPECIFICATIONS 5.4 FPDP Connector Pin Assignments The FPDP connector pin assignments are shown in . These assignments are the normal Table 5-1 (non-inverted) connector pin assignment for the FPDP interface described in Table 5-2 of the Front Panel Data Port Specifications, ANSI/VITA 17-1998. Cable conductor numbers are shown in parenthesis.
Page 44: Pin-Out On Pci Fibrextreme Carrier
SPECIFICATIONS 5.5 RS-232 Pin-out on PCI FibreXtreme Carrier The PCI FibreXtreme Carrier card’s RS-232 port uses an RJ-45 connector. Pin assignments are shown in Table 5-2. Table 5-2 PCI FibreXtreme Carrier Card’s RS-232 Pin Assignments Signal Direction Not Connected Not Connected Not Connected Not Connected A 14-foot RJ-45 straight cable and RJ-45 Female to DB-9 Female Adapter are provided with...
Page 45: Media Interface Specifications
SPECIFICATIONS 5.6 Media Interface Specifications 5.6.1 SL100 Fiber-Optic Media Interface Specifications Connector : ............. Duplex LC 850 nm: Media: ..........50 µm or 62.5 µm multi-mode fiber Fibre Channel Formats: ...... 100-M5-SN-I (1 Gbps, 50 µm fiber) 100-M6-SN-I (1 Gbps, 62.5 µm fiber) Maximum Fiber Length: .....
Page 46: Sl100 Hssdc2 Copper Media Interface
SPECIFICATIONS Receive Sensitivity: ......-18 to –3 dBm 1550 nm: Media: ..........8.3/125 µm single-mode fiber Maximum Fiber Length: ..... 26 km (max), 10 km (min) Transmit Wavelength: ......1500 to 1580 nm Transmit Power: ......... -2 to 3 dBm Receive Wavelength: ......
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Page 49 6. APPENDIX B - REGISTER SET TABLE OF CONTENTS 6.1 Overview ..........................6-1 6.1.1 Interrupt CSR (INT_CSR) – Offset 0x00 .............. 6-1 6.1.2 Board CSR (BRD_CSR) – Offset 0x04 ..............6-2 6.1.3 Link Control (LINK_CTL) – Offset 0x08 ............. 6-3 6.1.4 Link Status (LINK_STAT) –...
Page 51: Appendix B - Register Set
REGISTER SET 6.1 Overview The PCI FibreXtreme Carrier and SL240 rehostable CMC FPDP cards are designed so configuring the cards is as simple as possible. With minimal configuration, an SL240 FPDP card can transfer data between the link interface and the FPDP interface. This section describes the register set bit definitions.
Page 52: Board Csr (Brd_Csr) - Offset 0X04
REGISTER SET 6.1.2 Board CSR (BRD_CSR) – Offset 0x04 Description Access Reset Value Reserved None Reset – Write ‘1’ to reset the card. Writing ‘0’ has no affect. Reserved None JTAG TCK# – Controls the TCK# line on the JTAG port.
Page 53: Link Control (Link_Ctl) - Offset 0X08
Some exotic conditions could apply where flow control is not desirable, but they require very careful system planning and should be confirmed with Curtiss-Wright Controls prior to architectural finalization. One possible exception is for applications that cannot utilize a duplex fiber-optic link, which means status information (link up and state of flow control) is not available from the remote node.
Page 54 REGISTER SET Description Access Reset Value Reserved None Disable Receiver – A ‘1’ disables the link interface from placing data in the Receive FIFO. When set to ‘1,’ this signal also prevents the modification of the DIR, NRDY, and SUSPEND flags in the retransmitted data stream if Loop (Copy) Mode is enabled.
Page 55 REGISTER SET Description Access Reset Value topology (that is, two cards) because throughput will decrease by a factor related to frame size. 15 to 13 Reserved None Reset SR – Write ‘1’ to clear any latched status information from the registers. Writing ‘0’ has no effect.
Page 56: Link Status (Link_Stat) - Offset 0X0C
REGISTER SET 6.1.4 Link Status (LINK_STAT) – Offset 0x0C Description Access Reset Value 7 to 0 8B/10B Errors – This is an 8-bit counter counting the current number of 8B/10B decoding errors discovered. These bits are cleared through ‘Reset SR’ in LINK_CTL.
Page 57: Fpdp Flags (Fpdp_Flgs) - Offset 0X10
REGISTER SET 6.1.5 FPDP Flags (FPDP_FLGS) – Offset 0x10 Field Description Access Reset Value Send SYNC – Write ‘1’ to send SYNC without DVALID. Writing ‘0’ has no effect. PIO1 Out – State of the PIO1 line sent across the link. PIO2 Out –...
Page 58: Receive Fifo Threshold- Offset 0X14
REGISTER SET 6.1.6 Receive FIFO Threshold– Offset 0x14 NOTE: The lower 20 bits of this register, indicating the number of 32-bit words, is limited to showing a 4 MB value. This count value will decrement and roll over several times when reading data out of a full 128 MB receive FIFO.
Page 59 7. APPENDIX C - CARRIER/CMC CONFIGURATION TABLE OF CONTENTS 7.1 Overview ..........................7-1 7.2 PCI FibreXtreme Carrier Card Configuration Setup ..............7-2 7.3 PCI FibreXtreme Carrier Card Register Offsets ............... 7-3 7.3.1 PIO and Carrier Configuration – Offset 0x0 ............7-3 7.3.2 Reserved Register –...
Page 61: Appendix C - Carrier/Cmc Configuration
Some exotic conditions could apply where flow control is not desirable, but they require very careful system planning and should be confirmed with Curtiss-Wright Controls prior to architectural finalization. One possible exception is for applications that cannot utilize a duplex fiber optic link, which means status information (link up and state of flow control) is not available from the remote node.
Page 62: Pci Fibrextreme Carrier Card Configuration Setup
CARRIER/CMC CONFIGURATION 7.2 PCI FibreXtreme Carrier Card Configuration Setup To configure the cards, set up the environment shown in Figure 7-1. Connect an RS-232 cable from an RS-232-capable terminal to the RJ-45 connector on the PCI FibreXtreme Carrier card. Using a VT-100 terminal emulation program, configure the COM port with these settings: 9600 Baud, 8 data bits, 1 stop bit, no parity.
Page 63: Pci Fibrextreme Carrier Card Register Offsets
CARRIER/CMC CONFIGURATION 7.3 PCI FibreXtreme Carrier Card Register Offsets The carrier card registers bits are defined below. All register bits shown are readable and writable. The carrier card registers occupy offsets 0x0 to 0x3 on the carrier card. 7.3.1 PIO and Carrier Configuration – Offset 0x0 Description Reset Value...
Page 64: Cmc Configuration - Offset 0X2
CARRIER/CMC CONFIGURATION 7.3.3 CMC Configuration – Offset 0x2 Description Reset Value CRC Enable – If ‘Microcontroller Present’ is ‘0’, this value is ignored and the CMC register value is used. Set to ‘1’ to enable CRC checking/generation of link data. Set to ‘0’ to disable CRC checking/generation.
Page 65: Cmc Register Offsets
CARRIER/CMC CONFIGURATION 7.4 CMC Register Offsets The CMC registers are described in Appendix B, Register Set. 7.5 PCI FibreXtreme Carrier Configuration Commands The configuration software runs on the microcontroller on the carrier card. This software is accessed through a terminal emulation program. Eight configuration commands are available.
Page 66: Get Configuration (Gc )
CARRIER/CMC CONFIGURATION An example output from this command is shown below. SL100/SL240 FPDP VME Monitor v1.0 % ec 0 0 = 0C : 4 1 = 00 : 2 = 40 : 3 = 00 : 00 = 00000000 : 04 = 00000000 : 08 = 00000001 : 5 0C = 00000000 : _...
Page 67: Bus Read (Br
)
CARRIER/CMC CONFIGURATION configuration One of four possible register configurations identified as 0, 1, 2, or 3. 7.5.6 Bus Read (br <register set> <address>) This command reads directly from the carrier card’s registers and the CMC registers. This command is typically used only for debugging. The br command has the following parameters: register set carrier card’s registers.
Page 68: Pci Carrier Card Default Configurations
CARRIER/CMC CONFIGURATION 7.6 PCI Carrier Card Default Configurations Factory testing requires the configurations be set to some default values. These default configuration values are listed below. 7.6.1 Configuration 0 – FPDP-TM with CRC Disabled 0 = 0C 1 = 00 2 = 40 3 = 00 00 = 00000000...
Page 69: Configuration 3 - Fpdp-Rm With Crc Enabled
CARRIER/CMC CONFIGURATION 7.6.4 Configuration 3 - FPDP-RM with CRC Enabled 0 = 04 1 = 00 2 = 40 3 = 00 00 = 00000000 04 = 00000000 08 = 00000002 0C = 00000000 10 = 00000000 14 = 00000000 18 = 00000000 1C = 00000000 Copyright 2012...
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Page 71: Appendix D - Sl100/Sl240 Protocol
8. APPENDIX D - SL100/SL240 PROTOCOL TABLE OF CONTENTS 8.1 Overview ..........................8-1 8.2 Ordered Sets Used ........................8-1 8.3 Frames ............................8-3 8.3.1 Link Bandwidth ..................... 8-4 8.3.2 FPDP Signal Sample Rate ..................8-4 8.4 Data Transmission and Flow Control ..................8-5 TABLES Table 8-1 Ordered Set Mapping ........................
Page 73: Overview
SL100X/SL240X PROTOCOL 8.1 Overview The SL100/SL240 Serial FPDP protocol (also known as ANSI/VITA 17.1) is designed to provide near optimal throughput while maintaining low overhead. The link transfer rate for SL100 cards is 1.0625 Gbps, and the transfer rate for SL240 cards is 2.5 Gbps. Since an 8B/10B encoding scheme is used, this corresponds to a raw data rate of 106.25 MBps (1 MB = 10 bytes) for SL100 and 250 MBps for SL240.
Page 74: Table 8-1 Ordered Set Mapping
SL100X/SL240X PROTOCOL Table 8-1 Ordered Set Mapping Fibre Channel ANSI/VITA 17.1 Description Ordered Set Ordered Set SOFc1 Start of Frame: PIO1 = 0, PIO2 = 0, DIR = 0 SOFi1 Start of Frame: PIO1 = 0, PIO2 = 0, DIR = 1 SOFn1 Start of Frame: PIO1 = 0, PIO2 = 1, DIR = 0...
Page 75: Frames
SL100X/SL240X PROTOCOL 8.3 Frames There are four basic frame types defined in ANSI/VITA 17.1 - an IDLE frame, data frame, a SYNC without data frame, and a SYNC with data frame. The data is divided into frames so the FPDP signals are sampled at some minimum interval, and so the receiver is guaranteed to see IDLEs to maintain synchronization.
Page 76: Link Bandwidth
SL100X/SL240X PROTOCOL 8.3.1 Link Bandwidth With CRC disabled and the Copy Mode Master bit clear (‘0’), there is a five-word overhead for every frame transmitted. Since frames can contain up to 512 words of data, this results in an efficiency of 99.03%. With CRC enabled and the Loop Master bit clear, there is a six-word overhead for every frame transmitted.
Page 77: Data Transmission And Flow Control
GO—if it is STOP, then the data waits in the Transmit FIFO until the signal changes. Curtiss-Wright Controls’ SL100/SL240 cards use the same protocol when transmitting from either end to allow the link to operate bi-directionally.
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Page 79: Appendix E - Ordering Information
9. APPENDIX E - ORDERING INFORMATION TABLE OF CONTENTS 9.1 Overview ..........................9-1 9.2 Ordering Information ....................... 9-1 9.2.1 SL100 FPDP ......................9-1 9.2.2 SL240X FPDP ....................... 9-1 9.2.3 Carrier Card (without CMC) ................. 9-1 9.3 Media Interface ........................9-2 9.3.1 Short Wavelength: Multimode Fiber-Optic Cable ..........
Page 81: Overview
ORDERING INFORMATION 9.1 Overview This appendix contains the order number for all Curtiss-Wright Controls, Inc. products mentioned in this manual. For an up to date list, or for inquiries about these products, contact Curtiss-Wright Controls, Inc. Sales. 9.2 Ordering Information 9.2.1 SL100 FPDP...
Page 82: Media Interface
ORDERING INFORMATION 9.3 Media Interface 9.3.1 Short Wavelength: Multimode Fiber-Optic Cable The following table lists the order numbers for the simplex and duplex, 50/125 µm multimode fiber-optic cables, for use with the short wavelength laser media interface. Table 9-4 Multimode Fiber-Optic Cable (LC – LC) Simplex Duplex Length...
Page 83: Long Wavelength: Singlemode Fiber-Optic Cable
ORDERING INFORMATION 9.3.2 Long Wavelength: Singlemode Fiber-Optic Cable The following table lists the order numbers for the simplex and duplex, 9/125 µm singlemode fiber-optic cables, for use with the long wavelength laser media interface. Table 9-7 Singlemode Fiber-Optic Cable (LC –LC) Simplex Duplex Length...
Page 84: Hssdc2 Copper Media Interface: 2.5 Gbps
ORDERING INFORMATION 9.3.4 HSSDC2 Copper Media Interface: 2.5 Gbps Shielded 100-Ohm Shielded Quad copper cable with HSSDC2 (InfiniBand) connectors, for use with the HSSDC2 copper media interface. Table 9-10 Shielded 100-Ohm Quad Copper Cable with HSSDC2 (InfiniBand) Connectors Order Number Description FHAC-Q2H31000-00 1 m HSSDC2 cable, equalized...
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Page 87: Appendix F - Fpdp Primer
10. APPENDIX F - FPDP PRIMER TABLE OF CONTENTS 10.1 FPDP Overview ........................10-1 10.2 Terminology ......................... 10-3 10.2.1 FPDP Transmit Master (FPDP-TM) .................. 10-3 10.2.2 FPDP Receive Master (FPDP-RM) ................... 10-3 10.2.3 FPDP Receiver (FPDP-R) ....................10-3 10.3 Parallel FPDP Theory of Operation ..................10-3 10.3.1 Clock Signals ........................
Page 89: Fpdp Overview
FPDP PRIMER 10.1 FPDP Overview This appendix provides a brief discussion of Front Panel Data Port (FPDP). For more information about FPDP, refer to Front Panel Data Port Specifications, ANSI/VITA 17- 1998 or go to the VITA website at: www.vita.com/vso/. The SL100X/SL240X cards implement a serial version of FPDP on their link interface, which is standard ANSI/VITA 17.1.
Page 90 FPDP PRIMER FPDP-TM FPDP-R FPDP-R FPDP-R FPDP-R FPDP-RM Figure 10-1 Example Configuration with Multiple VME FPDP SL240 Carrier Cards Several advantages of an FPDP interface include: • Simple hardware is required to interface to FPDP. • FPDP does not interfere with the normal bus operations – VME or PCI traffic can continue without data transfers wasting bus bandwidth.
Page 91: Terminology
FPDP PRIMER Some additional advantages of parallel FPDP are: • Low cost, 32-bit parallel interface provided through a ribbon cable. • 160 MBps sustained data rate. Some additional advantages of Serial FPDP are: • Noise immune fiber-optic interface. • Significantly increased transmission distance (10 km). •...
Page 92 FPDP PRIMER /SYNC, was defined for framing purposes. The frame size is defined as the number of data items in the frame. Unframed data may also be transmitted onto the FPDP bus. The four data frame types defined by the FPDP specification are listed and described below. •...
Page 93: Serial Fpdp Theory Of Operation
FPDP PRIMER /DVALID are asserted. Since /SYNC is asserted at the end of a frame, the first data frame transmitted will not be synchronized. As a result, the system designer may wish to discard this first unsynchronized data frame. All data frames are the same size when fixed size repeating frame data is transmitted.
Page 94 FPDP PRIMER be double synchronized by the FPDP-TM before being used in order to avoid metastability problems. According to the Front Panel Data Port Specifications, ANSI/VITA 17-1998, the FPDP- TM transmits the Data Direction signal /DIR. FPDP-RM and FPDP-R devices may receive /DIR.
Page 95 FPDP PRIMER Figure 10-2 Parallel FPDP Interface Timing Diagram Copyright 2012 10-7 FibreXtreme HW Reference for FPDP Cards...
Page 96 FPDP PRIMER Figure 10-3 FPDP Timing Diagrams Showing the Use of Framing Copyright 2012 10-8 FibreXtreme HW Reference for FPDP Cards...
Page 97: Table 10-1 Parallel Fpdp Timing Specifications
FPDP PRIMER The timing parameters from Figures 10-2 and 10-3 are detailed in Tables 10-1 and 10-2. These timing specifications are taken from Front Panel Data Port Specifications, ANSI/VITA 17. Table 10-1 Parallel FPDP Timing Specifications Parameter Description At Transmitter At Receiver FPDP End of Cable...
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Page 99: Appendix G - Rehostable Cmc Fpdp Interface
11. APPENDIX G - REHOSTABLE CMC FPDP INTERFACE TABLE OF CONTENTS 11.1 Overview ..........................11-1 11.2 Mechanical Details ....................... 11-1 11.3 Terminology ......................... 11-2 11.4 CMC Mating Connectors ..................... 11-2 11.4.1 Configuration Signal Interconnects ..............11-3 11.4.2 Source Card Signal Interconnects ..............11-8 11.4.3 Destination Card Signal Interconnects.............
Page 100 FIGURES Figure 11-1 SL240 Rehostable CMC FPDP Card Dimensions ..............11-1 Figure 11-2 FPDP and SL240 Terminology ....................11-2 Figure 11-3 Signal Flow of PIO1, PIO2, DIR, and NRDY Through an SL100/SL240 CMC Card .... 11-9 Figure 11-4 RSTROBE Termination on the CMC Card ................11-12 Figure 11-5 Signal Flow of PIO1, PIO2, DIR, and NRDY Through an SL100/SL240 CMC Card ..
Page 101: Overview
REHOSTABLE CMC FPDP INTERFACE 11.1 Overview The SL240 rehostable CMC FPDP card is easily integrated into custom sensor and DSP hardware. This section details the electrical, mechanical, and thermal requirements for the CMC card. 11.2 Mechanical Details The SL240 rehostable CMC FPDP card is a single CMC as defined in IEEE P1386. There is one deviation from this standard on the card—it includes a P6 connector not listed in the specification.
Page 102: Terminology
The SL240 rehostable CMC card uses the 10 mm stacking height defined in IEEE P1386. There are several vendors for mating connectors for the CMC cards. Table 11-1 lists the connectors verified by Curtiss-Wright Controls to work correctly. Table 11-1 Connectors to Interface the SL240 Rehostable CMC Card...
Page 103: Configuration Signal Interconnects
SL240 rehostable CMC cards may be installed on a custom carrier card instead of on a Curtiss-Wright Controls PCI carrier card. This custom carrier card may use a microcontroller to access the SL240 CMC card’s register set. If a microcontroller is used, all pins listed in Table 11-2 must be used.
Page 104: Table 11-2 Fpdp Configuration Interface (P3)
REHOSTABLE CMC FPDP INTERFACE Table 11-2 FPDP Configuration Interface (P3) Input Output Input Output Lines Lines Lines Lines +3.3 V AD10 AD11 AD12 +3.3 V AD13 AD14 AD15 N.C. N.C. N.C. PECL_IN N.C. /PECL_IN N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Page 105: Table 11-3 Signal Descriptions For Fpdp Configuration Interface (P3)
REHOSTABLE CMC FPDP INTERFACE Table 11-3 Signal Descriptions for FPDP Configuration Interface (P3) Signal Name Signal Signal Description Direction AD[15:0] AD[15:8] are Register Address/Data Bus. This bus contains the address input of the desired register and one byte of this register's data. The bit definitions for reads/writes are: AD[7:0] are Bi-directional...
Page 106 Some exotic conditions could apply where flow control is not desirable, but they require very careful system planning and should be confirmed with Curtiss-Wright Controls prior to architectural finalization. One possible exception is for applications that cannot utilize a duplex fiber-optic link, which means status information (link up and state of flow control) is not available from the remote node.
Page 107 REHOSTABLE CMC FPDP INTERFACE Signal Name Signal Signal Description Direction indicates no interrupt has occurred. microcontroller Clock. This is the clock for the MCLK Input microcontroller interface. Its frequency should be less than 30 MHz and should never be disabled if the microcontroller interface is being used.
Page 108: Source Card Signal Interconnects
REHOSTABLE CMC FPDP INTERFACE 11.4.2 Source Card Signal Interconnects A source card for the system has to have the P3 interface and the P6 interface wired for operation. The P6 connector is the FPDP receiver interface. Table 11-4 lists the signal connections for the P6 connector. An asterisk “*” is used to designate signals that are common on the P4 and P6 connectors.
Page 109 REHOSTABLE CMC FPDP INTERFACE Figure 11-3 Signal Flow of PIO1, PIO2, DIR, and NRDY Through an SL100/SL240 CMC Card Copyright 2012 11-9 FibreXtreme HW Reference for FPDP Cards...
Page 110: Table 11-4 Fpdp Receiver Interface (P6)
REHOSTABLE CMC FPDP INTERFACE Table 11-4 FPDP Receiver Interface (P6) Input Output Input Output Lines Lines Lines Lines PIO2_IN* PIO2_OUT* +5 V PIO1_IN* RERROR PIO1_OUT* /RNRDY /RSUSPEND RSTROBE /RDVALID /RESET* RESERVED /RDIR /RSYNC RESERVED RD31 +5 V RD30 RD29 RD28 RD27 RD26 RD25...
Page 111: Table 11-5 Signal Descriptions For Fpdp Receiver Interface (P6)
REHOSTABLE CMC FPDP INTERFACE Table 11-5 Signal Descriptions for FPDP Receiver Interface (P6) Signal Name Signal Signal Description Direction RD[31:0] Input Receive Data Bus. This is data from the FPDP interface to the Transmit FIFO of the SL240 card. It is placed in the Transmit FIFO on a rising edge of RSTROBE with /RDVALID asserted.
Page 112: Destination Card Signal Interconnects
REHOSTABLE CMC FPDP INTERFACE P6 CMC RSTROBE FPGA Connector 51 Ω 0.1 µF Figure 11-4 RSTROBE Termination on the CMC Card 11.4.3 Destination Card Signal Interconnects A destination card for the system must have the P3 interface and the P4 interface wired for operation.
Page 113 REHOSTABLE CMC FPDP INTERFACE NOTE 2: /TDIR, PIO1_OUT, PI02_OUT, and /RNRDY are decoded from the Serial FPDP data stream by the decoder logic and are latched based on the last value received by the data stream. These signals do not propagate through the Receive FIFO within the SL100/SL240 CMC card and thus cannot be directly associated with the corresponding data.
Page 114: Table 11-6 Fpdp Transmitter Interface (P4)
REHOSTABLE CMC FPDP INTERFACE Table 11-6 FPDP Transmitter Interface (P4) Input Output Input Output Lines Lines Lines Lines N.C. N.C. +5 V +5 V TD10 TD11 TD12 TD13 TD14 TD15 TD16 TD17 TD18 TD19 +5 V +5 V TD20 TD21 TD22 TD23 TD24...
Page 115: Table 11-7 Signal Descriptions For Fpdp Transmitter Interface (P4)
REHOSTABLE CMC FPDP INTERFACE Certain signals are important for the transmitter interface, while others are important only for the receive interface. In the following signal descriptions, a ‘1’ refers to a logic high level (above 2.0 V), while a ‘0’ refers to a logic low level (less than 0.8 V). All signals use the LVTTL Input/Output standard.
Page 116: Programmed Inputs/Outputs (Pios)
REHOSTABLE CMC FPDP INTERFACE Signal Name Signal Signal Description Direction TSTROBE Output FPDP Transmitter Clock Output. This is a clock-divided version of the reference clock (53.125 MHz or 125 MHz). This clock’s frequency is determined by CLK_CFG[1:0]. All signals sent to the FPDP interface are synchronized to this clock.
Page 117: Thermal Specifications
REHOSTABLE CMC FPDP INTERFACE 11.6 Thermal Specifications The SL240 rehostable CMC card stays within the thermal specifications of IEEE P1386. Airflow is recommended for the card, though operation at 0 to 50°C ambient is feasible without airflow. Components on this card may become very warm during operation. Care should be taken to ensure this does not disturb other cards in the system.
Page 118: Ac Characteristics
REHOSTABLE CMC FPDP INTERFACE 11.7.2 AC Characteristics Table 11-9 and Table 11-10 contain the major timing components involved with interfacing the SL240 rehostable CMC card. Table 11-9 provides timing parameters for the source side. Table 11-10 provides timing parameters for the destination side. Bi- directional cards must meet the timing parameters in both Table 11-9 and Table 11-10.
Page 119: Transmitting Data
REHOSTABLE CMC FPDP INTERFACE 11.8 Transmitting Data Data is transmitted through the FPDP interface. Figure 11-7 shows the timing for a few of these transactions. In addition to this appendix, see Appendix F, FPDP Primer, for details about these signals. Figure 11-7 Parallel FPDP Interface Timing Diagram Copyright 2012 11-19...
Page 120: Microcontroller Interface
REHOSTABLE CMC FPDP INTERFACE Table 11-11 FPDP Transmitter Interface Timing Parameters Parameter Description Data, /DVALID, /SYNC 5 ns setup time Data, /DVALID, /SYNC hold 0 ns time /SUSPEND asserted to data 16 clocks stop /SUSPEND de-asserted to 1 clock data started 11.9 Microcontroller Interface The microcontroller interface on the SL240 CMC card is used to access the internal control and status registers.
Page 121 REHOSTABLE CMC FPDP INTERFACE To write to the registers, three clock cycles are needed. The first clock cycle is used to transfer the address to the CMC card. The second clock cycle has no operation assigned to it, and is left unused to remain consistent with the read operation. On the third clock, the data is actually written to the register.
Page 123: Appendix G - Rehostable Cmc Fpdp Interface
REHOSTABLE CMC FPDP INTERFACE Copyright 2012 11-23 FibreXtreme HW Reference for FPDP Cards...

This manual is also suitable for:

Fibrextreme sl240 Fibrextreme sl240x Fhk4-fm4mwb04-00 Fhk6-fm6mwb04-00

Curtiss-Wright FibreXtreme SL100 Hardware Reference Manual

1 Introduction

2 Product Overview

3 Installation

4 Operation

5 Appendix A - Specifications

Appendix A - Specifications

6 Appendix B - Register Set

Appendix B - Register Set

7 Appendix C - Carrier/CMC Configuration

Appendix C - Carrier/CMC Configuration

Appendix D - Sl100/Sl240 Protocol

8 Appendix D - Sl100/Sl240 Protocol

9 Appendix E - Ordering Information

Appendix E - Ordering Information

10 Appendix F - Fpdp Primer

Appendix F - Fpdp Primer

11 Appendix G - Rehostable CMC Fpdp Interface

Appendix G - Rehostable CMC Fpdp Interface

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