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Teledyne ADQ8-4X Manual

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Manual ADQ8-4X
This manual describes how to get the full potential out of Teledyne SP Devices'
digitizer ADQ8-4X. The manual includes these steps:
•
Set up the analog front-end
•
Master the triggers
•
Control the acquisition
•
Manage the sampling clock
•
Understanding data transfer to host PC
•
Using GPIO
Teledyne Signal Processing Devices Sweden AB | Teknikringen 6, SE-583 30 Linköping, Sweden | www.spdevices.com
Regional sales offices | www.spdevices.com/contact
ADQ8-4X Manual
19-2302 A 2020-09-16
1(46)

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Summary of Contents for Teledyne ADQ8-4X

  • Page 1 Master the triggers • Control the acquisition • Manage the sampling clock • Understanding data transfer to host PC • Using GPIO Teledyne Signal Processing Devices Sweden AB | Teknikringen 6, SE-583 30 Linköping, Sweden | www.spdevices.com Regional sales offices | www.spdevices.com/contact...

  • Page 2: Table Of Contents

    1.2.6 Analog signal range ........................7 Digitizer Studio overview....................8 SETTING UP THE ANALOG FRONT-END ..............9 ADQ8-4X AFE block diagram ..................9 Set analog input range....................9 Set analog DC-offset....................10 Adjusting the digital gain and offset ................10 SIGNAL QUALITY ENHANCEMENT................
  • Page 3 Clock reference output....................32 5.10 Sample skip ......................... 32 GPIO ..........................33 GPIO on TRIG connector..................... 33 ADQ8-4X–PXIe GPIO on SYNC connectors ............... 34 Using GPIO as a trigger....................34 Output .......................... 34 GPIO in ADQ Development Kit ..................34 ACQUISITION CONTROL ...................
  • Page 4 ADQ8-4X Manual 19-2302 A 2020-09-16 4(46) REFERENCES ......................45 19-2302 A 2020-09-16 4(46)

  • Page 5: Introduction

    Data format The ADC components of ADQ8-4X has 10 bits resolution, while the data format inside the ADQ8-4X and out to the host PC is 16 bits. The 16 bits from the ADCs are MSB aligned in this 16 bit data word.

  • Page 6: Calibration

    1.2.4 Sampling clock frequency The ADQ8-4X is designed for the specified 2 GHz clock frequency only with the firmware FWDAQ. The firmware FW4GDAQ enables sampling at 4 GSPS. A different sampling rate can be achieved by using the sample skip function, Section 5.10.

  • Page 7: Analog Signal Range

    ADQ8-4X Manual 19-2302 A 2020-09-16 7(46) All other interfaces operate on the data processing clock of the FPGA at 250 MHz. This clock is referred to as the Data Clock. Section 5.1 for more details on the clock system. 1.2.6...

  • Page 8: Digitizer Studio Overview

    8(46) 1.3 Digitizer Studio overview The application software Digitizer Studio is an easy way to operate the ADQ8-4X. Digitizer Studio is a graphical interface. The different blocks of the ADQ digitizer are represented by several views in Digi- tizer Studio. These blocks are linked as in Figure 2.

  • Page 9: Setting Up The Analog Front-End

    Figure 3: AFE control. 2.2 Set analog input range On ADQ8-4X–VG, the input range is variable. The requested input signal range is sent to the API, which reads available settings and return the best selection. The actual value of each range is available...

  • Page 10: Set Analog Dc-Offset

    ADQ8-4X Manual 19-2302 A 2020-09-16 10(46) A specific code then represent the analog level as: DIGITAL_CODE_LEVEL ANALOG_LEVEL = ( DIGITAL_CODE_LEVEL / 2^15 ) * ( ACTUAL_ANALOG_RANGE / 2) 2.3 Set analog DC-offset A user-controlled DC-offset is available. The analog DC-offset is applied to the signal to better adopt to the signal range of the digitizer.

  • Page 11: Signal Quality Enhancement

    ADQ8-4X Manual 19-2302 A 2020-09-16 11(46) SIGNAL QUALITY ENHANCEMENT 3.1 Digital Baseline Stabilizer The Digital Baseline Stabilizer, DBS, is designed for pulse data measurement where high accuracy rel- ative a known baseline is required. The key features of DBS are: •...

  • Page 12: Trigger

    ADQ8-4X Manual 19-2302 A 2020-09-16 12(46) TRIGGER 4.1 Trigger block diagram 34  "&  (   34   $  % &   '() 34 % &     * #     '()    * # ...

  • Page 13: Introduction

    ADQ8-4X Manual 19-2302 A 2020-09-16 13(46) 4.2 Introduction The digitizer can be triggered in various ways with a number of different internal and external trigger sources. Selected events in the trigger module can also be output to trigger external equipment. The...

  • Page 14: Timestamp

    Example 3: Assume an ADQ8-4X sampling with a clock frequency at 2 GSPS. The pretrigger is set to 32 samples and the external trigger is used. The following parameters are returned:...
  • Page 15 ADQ8-4X Manual 19-2302 A 2020-09-16 15(46) 1. The timestamp counter is reset at power-up. This methods does not, however, have absolute preci- sion, since the timing of the power up is not defined. In a multi-board system, the timestamp will dif- fer between the boards.

  • Page 16: Blocking Triggers For Synchronization

    ADQ8-4X Manual 19-2302 A 2020-09-16 16(46) +,   -./ %   +,   %01     & '                  DESCRIPTION USER COMMAND External trigger input signal on front panel connector.
  • Page 17 ADQ8-4X Manual 19-2302 A 2020-09-16 17(46) Figure 9 illustrates how the triggers are accepted or rejected in the window mode. /0  12.       "3  /0  45 63  7  "3 ...

  • Page 18: Block Triggers Once

    ADQ8-4X Manual 19-2302 A 2020-09-16 18(46) '  $ ) *& !&  % !   + ,  % !   +,  % !   +,  % !   + , DESCRIPTION USER COMMAND The trigger blocker in window or gate mode allows triggers during a SetupTriggerBlocking 4.5.1 certain period. Example of rejected triggers outside the window.

  • Page 19: Trigger Jitter

    The RMS value of such a process is /sqrt(12). TRIGGER_CLOCK_PERIOD The highest resolution is achieved with an external trigger connected to the TRIG connector. ADQ8-4X has a trigger clock at 4 GSPS, of 250 ps and a trigger jitter of TRIGGER_CLOCK_PERIOD 72 ps RMS (theoretical value), Section 4.6.4.

  • Page 20: Synchronous Trigger

               Figure 11: Extended trigger resolution timing for ADQ8-4X The position of the first sample is rounded up from the trigger position. The parameter RECORD_START tells where the trigger was. Referring to...

  • Page 21: External Trigger Inputs

    ADQ8-4X Manual 19-2302 A 2020-09-16 21(46) DisArmTrigger (“software trigger”) SetTriggerMode ArmTrigger SWTrig 6. Read data and analyze the situation 4.8 External Trigger Inputs An external trigger is a dedicated signal on a dedicated input to the ADQ. There are several inputs for...

  • Page 22: External Trigger Sync Connector

    ADQ8-4X Manual 19-2302 A 2020-09-16 22(46) 4.8.2 External trigger SYNC connector The block diagram for the SYNC input is shown in Figure 13 and related parameters are listed in Table 2. The user can control the SYNC function for adapting it to the system in the following ways: The input impedance can be set in 50 ...

  • Page 23: External Trigger In The Backplane

    ADQ8-4X Manual 19-2302 A 2020-09-16 23(46) )*+) *,$ )*+) *,$ )*+) *,$ )*+) *,$ -.#! "  )*+) *,$ *#!   /#0 -.#!   #!   Figure 14: Bussed connections 4.9 External trigger in the backplane 4.9.1 PXIe interface There are an external trigger in the backplane of the PXIe version. The DSTAR signals are dedicated matched trigger lines from the system timing slot.

  • Page 24: Level Trigger

    ADQ8-4X Manual 19-2302 A 2020-09-16 24(46) %  * +, - +, - !+ , !+ ,% !+ , % * * DESCRIPTION USER COMMAND Backplane Trigger bus and DSTAR connections Set direction for each port in the backplane SetDirectionPXI...

  • Page 25: 1Setting The Level Trigger Level

    ADQ8-4X Manual 19-2302 A 2020-09-16 25(46)      )    * $ DESCRIPTION USER COMMAND When the signal passes the trigger level, a trigger event is generated and SetupLevelTrigger 4.10.1 the first record is captured.

  • Page 26: Internal Trigger

    ADQ8-4X Manual 19-2302 A 2020-09-16 26(46)    DESCRIPTION USER COMMAND The level trigger has a hysteresis function to avoid false triggering on 4.10.3 noise. When the signal passes below the RESET_LEVEL_CODE, the ADQ may trigger again.

  • Page 27: 3Triggering External Equipment With Internal Trigger

    ADQ8-4X Manual 19-2302 A 2020-09-16 27(46) The frame sync count triggers and output a signal at a certain period. The period is measured in trigger events. 4.12.3 Triggering external equipment with internal trigger Triggering external equipment and the digitizer with the internal trigger may be done in two ways; inter-...

  • Page 28: Large Scale Integration Trigger Support

    Figure 19: External routing of internal trigger. 4.13 Large scale integration trigger support The ADQ8-4X supports integration into a large scale PXIe chassis for single shot applications, The function is described in the manual [6]. This section is only a short introduction.
  • Page 29 ADQ8-4X Manual 19-2302 A 2020-09-16 29(46) 123 &0 # &#$ 123 "  $ $ .#   # $ 0 $ $  /. 123 "  $ $ .#   # $ 0  $$#  /.

  • Page 30: Clock

    ADQ8-4X Manual 19-2302 A 2020-09-16 30(46) CLOCK 5.1 Clock domains Different parts of the digitizer system operate on different clocks. The core of the clocking system is the clock reference. This is the phase and frequency reference of the digitizer system. It is possible to use different clock reference sources to meet the requirements of different applications.

  • Page 31: Adq8-4X-Pcie Front Panel Connectors

    The digitizer supports its specified sample rate only. This sample rate can be tuned to allow phase locking to external equipment. To reduce the sample-rate, a sample skip function is available. Block diagram of the clock network for ADQ8-4X-PXIe is given in Figure #2 * ./0...

  • Page 32: Clock Reference Phase Tuning

    ADQ8-4X Manual 19-2302 A 2020-09-16 32(46) The connector on the front panel accepts a clock reference from external equipment. The clock refer- ence quality is improved in a jitter cleaning circuitry. To match the tuning of the jitter cleaning circuitry the clock reference has to be 10 MHz.

  • Page 33: Gpio

    ADQ8-4X Manual 19-2302 A 2020-09-16 33(46) GPIO The General Purpose Input and Output (GPIO) are digital signals available from the front panel of the digitizer. The GPIO is an optional use of the TRIG and SYNC connectors. The user assigns a function to these pins, either in the firmware through the ADQ Development Kit or from software.

  • Page 34: Adq8-4X-Pxie Gpio On Sync Connectors

    19-2302 A 2020-09-16 34(46) 6.2 ADQ8-4X–PXIe GPIO on SYNC connectors On the ADQ8-4X–PXIe form factor, the sync input pin and output pins are split into two connectors. This means that the sync pin is not bi-directional when used as GPIO, Figure...

  • Page 35: Acquisition Control

    ADQ8-4X Manual 19-2302 A 2020-09-16 35(46) ACQUISITION CONTROL The acquisition control consists of two partly independent parts; • Acquisition process: acquisition of data in a record int the DRAM of the digitizer • Transfer process: transfer data from the DRAM of the digitizer to host PC.

  • Page 36: Triggered Streaming Acquisition

    Triggered streaming is described in [7]. 7.4 Acquisition mode multi-record ADQ8-4X supports acquisition mode multi-record. This mode is suitable for most user-scheduled single shot or multi-shot applications. It is also suitable for control and surveillance applications where the long pre-trigger makes it possible to see what preceded an event.

  • Page 37: Re-Arm Time

    ADQ8-4X Manual 19-2302 A 2020-09-16 37(46) ," ," )  + + +- ," )  )  Figure 27: Multi-record organization of memory.    %    $  %   Figure 28: Multi-record timing. 7.5 Re-arm time The re-arm time a the time after a record has been completely acquired when the digitizer cannot receive a new trigger.

  • Page 38: User Scheduled Data Transfer Mode

    ADQ8-4X Manual 19-2302 A 2020-09-16 38(46) )&  )&       *+ ,    -    )&  )&      "    *.+ "   )&          * +    Figure 29: Re-arm timing.
  • Page 39 ADQ8-4X Manual 19-2302 A 2020-09-16 39(46) 2#' 3 2# # # )   " 001 %  # # %" # "" !  2) # # !  2) # # -"  $ * + , * + ##  " #"  "  ...

  • Page 40: Transfer Buffers

    ADQ8-4X Manual 19-2302 A 2020-09-16 40(46) '  *  '  *  $ '  *  7 '  *       Figure 31: Timing of user-scheduled data transfer.

  • Page 41: Record Header

    ADQ8-4X Manual 19-2302 A 2020-09-16 41(46) .    . +  "/ 0 "2 1  1     .    .    . +  "/ 0 "2 1  1  1  2345       .

  • Page 42: User Id

    ADQ8-4X Manual 19-2302 A 2020-09-16 42(46) FIFO fill factor is indicated. This is useful when tuning a data-driven process to avoid FIFO overflow and still get maximum efficiency from the experiment. For very long records, the maximum fill factor during the record is given.

  • Page 43: Over-Range And Under-Range

    ADQ8-4X Manual 19-2302 A 2020-09-16 43(46) 7.10 Over-range and under-range The over/under-range bit in the header indicates that over-range or under-range occurred at one or several samples within the record and at any stage in the signal chain. The result of the over-range is...

  • Page 44: Host Pc Connection

    ADQ8-4X Manual 19-2302 A 2020-09-16 44(46) HOST PC CONNECTION 8.1 PCI Express interface The MTCA, and PXIE versions of the digitizer use PCI Express generation 1 and 2 electrical interface to communicate with the host PC. The PCIe version of the digitizer support up to 8 lanes and the MTCA version support up to 4 lanes.
  • Page 45 ADQ8-4X Manual 19-2302 A 2020-09-16 45(46) REFERENCES 17-1998 ADQ8-4X Datasheet 14-1351 ADQAPI Reference guide 08-0214 ADQAPI User guide 18-2059 ADQUpdater user guide 20-2382 Digitizer Studio manual 19-2246 ADQ8 Daisy-Chain Board synchronization 20-2465 ADQ8 Triggered streaming 19-2302 A 2020-09-16 45(46)
  • Page 46 Buyer shall not return any products for any reason without the prior written authorization of Teledyne SP Devices. In no event shall Teledyne SP Devices be liable for any damages arising out of or related to this docu- ment or the information contained in it.

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