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Service Information
Multiplexer relay power control
A relay power control circuit, made up of U114, U115,
Q100, Q101, and associated components, keeps power dissi-
pated in relay coils at a minimum, thus reducing possible
problems caused by thermal EMFs.
During steady-state operation, the relay supply voltage, +V,
is regulated to +3.5V to minimize coil power dissipation.
When a relay is first closed, the STROBE pulse applied to
U114 changes the parameters of the relay supply voltage reg-
ulator, Q100, allowing the relay supply voltage, +V, to rise to
+5.7V for about 100msec. This brief voltage rise ensures that
relays close as quickly as possible. After the 100msec period
has elapsed, the relay supply voltage (+V) drops back down
to its nominal steady-state value of +3.5V.
Digital I/O output channel control
Digital output channels are controlled by serial data trans-
mitted from the mainframe to the card via the OUTDATA
line. A total of two bytes are shifted in a serial fashion into
latches located in the output channel driver ICs. The serial
data is clocked in by the OUTCLK line. As data overflows
one register, it is fed out the Q's line of the register down the
chain.
Once all bytes have shifted into the card, the STROBE line
is set high to latch the output channel information into the Q
outputs of the output channel drivers. Note that a channel
driver output can go low or high when it is turned on (closed)
depending on its logic configuration.
Digital I/O input channel control
The mainframe reads digital input channels of the I/O card
from a serial, two-byte data stream (via INDATA line).
Digital inputs are applied in a parallel fashion to the two in-
put channel registers (U102 contains eight channels and
U101 contains two channels). When the digital inputs are
read, the STROBE line goes high to latch the input channel
information. The INCLOCK line then clocks out the infor-
mation as a serial, two-byte data stream (via INDATA line)
to the mainframe. As data empties from the lead register
(U101), it is replaced by data via the Q7 line of the registers
down the chain.
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Power-on safeguard
NOTE
The power-on safeguard circuit discussed
below is actually located on the digital
board in the mainframe.
A power-on safeguard circuit, made up of a D-type flip-flop
and associated components ensures that relays and digital I/O
output channels do not randomly energize on power-up and
power-down. This circuit disables all relays and output chan-
nels (all relays and output channels are open) during power-
up and power-down periods.
The PRESET line on the D-type flip-flop is controlled by the
68302 microprocessor, while the CLK line of the D-type
flip-flop is controlled by a VIA port line on the 68302 proces-
sor. The Q output of the flip-flop drives each card relay/out-
put channel driver IC enable pin (U105-U109, pin 8).
When the 68302 microprocessor is in the reset mode, the
flip-flop PRESET line is held low, and Q out immediately
goes high, disabling all relays and output channels (driver IC
enable pins are high). After the reset condition elapses
(≈200msec), PRESET goes high while Q out stays high.
When the first valid STROBE pulse occurs, a low logic level
is clocked into the D-type flip-flop, setting Q out low and en-
abling all relay drivers and output channel drivers simulta-
neously. Note that Q out stays low, (enabling relay drivers
and output channel drivers) until the 68302 processor goes
into a reset condition.
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Troubleshooting
