Comparison To Escc Family - CommTech FASTCOM SuperFASTCOM Hardware Reference Manual

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SuperFASTCOM / ESCC FAMILY COMPARISON
Enhancements to the ESCC Serial Core
The SuperFASTCOM adapter contains the core logic of the ESCC2 V3.2A as the heart of the
device. Some enhancements are incorporated in the SuperFASTCOM. These are:
16-Kbyte packet length byte counter
Enhanced address filtering (16-bit maskable)
Enhanced time slot assigner
Support of high data rates (45 Mbit/s for DS3 or 52 Mbit/s for OC1). Protocol support is
limited to HDLC Sub-modes without address recognition.
Simplifications of the ESCC Serial Core
The following features of the ESCC core have been removed:
SDLC Loop mode
Extended transparent mode 0 (this mode provided octet buffered data reception without
usage of FIFOs; the SuperFASTCOM supports octet buffered reception via appropriate
threshold configurations for the SCC receive FIFOs)