When Using External Input For Lvdd And Uvdd3; Uart/Spi Settings; Uart Mode; Spi Mode - Epson S1R72U06 Manual

9.3.2 When using external input for LVDD and UVDD3

(Select blue settings)
No.
JP9 U06 internal regulator input capacitor
JP10 LVDD external input selection
JP11 U06 internal regulator enable switching
JP12 U06 internal regulator input capacitor
JP13 UVDD3 external input selection
Note: External input will be +3.3 V for UVDD3 and +1.8 V for LVDD.
9.4

UART/SPI settings

Set UART/SPI mode as shown below when connected to the main CPU.
For more information, refer to the S1R72U06 Technical Manual.
9.4.1

UART mode

(1) Mode setting : Set SW1 (SPIxUART) to 1-2 (Low).
(2) Initial baud rate : Set SW4 (INIT_BAUD) to 1-2 (300 bps) or 2-3 (9,600 bps).
(3) Other : Set CN9-5-pin (SCK) to Low. The CN9-7-pin (SS) can be used to control MISO pin
output.
9.4.2

SPI mode

(1) Mode setting
(2) Other
Note: SW4 (INIT_BAUD) is not used in SPI mode, since this is a dedicated UART setting. We recommend
setting this to Low.

9.5 CLKIN

The following procedures are required when feeding clock input to the S1R72U06 CLKIN pin with this board:
(1) Remove CR1.
(2) Set JP8 to Open. (When CLKSEL = 24 MHz)
(3) Remove C23, C24, R30, R22, R23.
(4) Mount 100 k on R64.
(5) Connect CR1-1 pin side (IC4 XI pin side) of C23 to GND via a jumper. Leave the XO pin open.
(6) Input clock to TP6 (CLKIN).
Note: Set the input clock amplitude for the CLKIN pin to the same voltage as selected for CVDD with JP3.
S1R72U06 Evaluation Board Manual
(Rev.1.0)
Content
: Set SW1 (SPIxUART) to 2-3 (High).
: Set SW4 (INIT_BAUD) to 1-2 (Low).
Open With LVDD external input
Short When using U06 internal regulator
Open When using U06 internal regulator
Short With LVDD external input
1-2 Disable
1-3 Enable
Open With UVDD3 external input
Short When using U06 internal regulator
Open When using U06 internal regulator
Short With UVDD3 external input
EPSON
9. Setting Example
Setting
13