Entire Design Of The I²C-Bus - JUMO CEROS S01 M Interface Description

Digital pressure measuring cell
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2 I²C - communication
2.2.3
Entire design of the I²C-bus
The following figure shows a entire design by way of example, including a master, three digital pressure
measuring cells as slaves and pull-up resistors. The signal wires SDA and SCL are connected by pull-
up resistors to U
data rate or low power consumption, other resistance values are possible.
Scheme of a I²C-bus structure:
R
Pullup
R
Pullup
U
SCL
B
μC
Master
I²C is designed as a Master-Slave-bus. A data transfer is initiated by a master and the slave, which is
addressed, reacts on it. Every slave in a bus structure needs a different address to avoid collisions. The
address is stored in the memory of the device. For the communication between master and slave the
bus needs two signal wires: SCL as a clock wire and SDA as a data wire.
Every device connected to SCL and SDA has an open-collector-output. Combined with the pull-up re-
sistors it results in a wired-and circuit. Additional series resistors can be placed directly at the devices to
get more security.
The I²C-bus has a positive logic, what means that a high level at SDA corresponds to a logical '1' and a
low level corresponds to a logical '0'.
The transmission protocol of I²C starts with a start-bit, the address and a R/W- bit (Read/Write) sent by
the master. This will be confirmed by the addressed slave with an ACK-bit. Dependent on the R/W-bit
data is written (data to slave) or read (data to master). The confirmation with the ACK-bit is sent by the
slave when writing and by the master when reading. The last byte of a reading access is confirmed with
a NACK-bit by the master, to show the end of a transmission. The transmission is finished with a stop-bit.
The bit rate of the data transfer is set by the master.
The maximum bit rate, supported by the digital pressure measuring cell, is shown in the following chap-
ter.
8
. A pull-up resistor in the range of 1 to 10 kΩ is recommended. In order to optimize the
B
SDA
0V
Addr: 0x29
Addr: 0x28
1st slave
Addr: 0x2A
Addr: 0x28
2nd slave
Addr: 0x2B
Addr: 0x28
nth slave

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