Pcm Timing Information - Laird BT830-SA Hardware Integration Manual

BT830 Hardware Integration Guide
Version 1.3

PCM Timing Information

Table 10: PCM Timing information
Symbol Parameter
f
mclk PCM_CLK frequency
-
PCM_SYNC frequency for SCO connection
t (a)
mclkh PCM_CLK high
t a)
mclkl PCM_CLK low
-
PCM_CLK jitter
Delay time from
t
PCM_CLK high to
dmclksynch
PCM_SYNC high
t
dmclkpout Delay time from PCM_CLK high to valid PCM_OUT
Delay time from
PCM_CLK low to
t
dmclklsyncl
PCM_SYNC low (long
frame sync only)
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Table 11: PCM Master Mode Timing Parameters
Symbol
t
dmclkhsyncl
t
dmclklpoutz
t
dmclkhpoutz
t
supinclkl
t
hpinclkl
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4MHz DDS generation. Frequency
selection is programmable.
48MHz DDS generation. Frequency
selection is programmable.
4MHz DDS generation
4MHz DDS generation
48MHz DDS generation
4MHz DDS generation
48MHz DDS generation
4MHz DDS generation
48MHz DDS generation
Parameter
Delay time from
PCM_CLK high to
PCM_SYNC low
Delay time from PCM_CLK low to PCM_OUT
high impedance
Delay time from PCM_CLK high to PCM_OUT
high impedance
Set-up time for PCM_IN valid to PCM_CLK low
Hold time for PCM_CLK low to PCM_IN invalid
4MHz DDS generation
48MHz DDS generation
17
Min Typ Max
128
- 256 -
512
2.9 - -
- 8 -
980 - -
730 - -
- - 21
- - 20
- - 40.83
- - 20
- - 20
- - 40.83
Min Typ Max Unit
- - 20 ns
- - 40.83 ns
- - 20 ns
- - 20 ns
20 - - ns
0 - - ns
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Unit
kHz
kHz
kHz
ns
ns
ns
pk-pk
ns
ns
ns
ns
ns