Pioneer PDP-425CMX Service Manual page 179

5
Pin Function
No. Pin Name
*A AnP
*B AnM
Rn,Gn,Bn,
*C
DE,HSYNC,
69/71/70
VSYNC
91 RxCLK INP
92 RxCLK INM
42 RxCLK OUT
77 R_FDE
5 PLLSEL
6 BAL
4 DESKEW
78 PD
73 STOPCLK
*D V
CC
*E GND
2 PLLV
CC
1, 3 PLLGND
81, 93 LVDSV
CC
LVDSGND
76, 88, 100
75 CNTLE,
CNTLF
74
Note 1 : The DS90CF388 is designed to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90C387 and deserialize the LVDS
data according to the defined bit mapping.
[Pin No.]
*A : 79, 82, 84, 86, 89, 94, 96, 98
*B : 80, 83, 85, 87, 90, 95, 97, 99
*C : 8–12, 14, 15, 17–22, 24, 26–32, 34, 36–41, 43, 46–53, 55, 57–62, 64, 65, 67, 68
*D : 13, 23, 33, 45, 56, 66
*E : 7, 16, 25, 35, 44, 54, 63, 72
5
6
I/O
I Positive LVDS differential data inputs.
I Negative LVDS differential data inputs.
O TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3
control lines – HSYNC (LP), VSYNC (FLM), DE (Data Enable).
I Positive LVDS differential clock input.
I Negative LVDS differential clock input.
O TTL level clock output. The falling edge acts as data strobe.
I Programmable control (DE) strobe select. Tied high for data active when DE
is high.
I PLL range select. This pin must be tied to V
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz.
I Mode select for DC Balanced (new) or non-DC Balanced (backward
compatible) interface. BAL = LOW fornon-DC Balanced mode. BAL = HIGH
for DC Balanced Mode (Auto-detect mode), with this pin HIGH the received
LVDS clock signal is used to determine if the interface is in new or backward
compatible mode (Notes 1) .
I Deskew and oversampling "on/off" select. Deskew is active when in put is
high. Only supported in DC Balance mode (BAL = High). To complete the
deskew operation, a minimum of four clock cycles is required during
blanking time.
I TTL level in put. When asserted (low input) the receiver data outputs are low
and clock out put is high.
O Indicates receiver clock in put signal is not present with a logic high. With a
clock input present, alow logic is indicated.
I Power supply pins for TTL outputs and digital circuitry.
I Ground pins for TTL outputs and digital circuitry
I Power supply for PLL circuitry.
I Ground pin for PLL circuitry.
I Power supply pin for LVDS inputs.
I Ground pins for LVDS in puts.
O TTL level data outputs. User-defined control signals - no connect when not
used.
PDP-425CMX
6
7
Description
for auto-range. NC or tied to
CC
7
8
A
B
C
D
E
F
179
8