Pioneer PDP-5071PU Service Manual page 206

1
Pin Function
A
2.5 Clock generator terminal
Acronyms Terminal
number
XI 55
XO 54
BCLK8 102
B
µ
2.6 Terminal for PD64031A and
Acronyms Terminal
number
FCLK8 78
C
FCKQ 127
FOCP 128
D
2.7 Terminal for RGB input
Acronyms Terminal
number
DFBI 130
DYSI 131
E
DYMI 134
DCGI 135
DCBI 136
DCRI 137
FCSI 129
F
206
1
2
I/O Level Buffer type
PU/PD [kΩ]
I Analog –
O Analog –
I/O LVTTL 6 mA
3-state
µ
PD64032 digital connection
I/O Level Buffer type
PU/PD [kΩ]
I/O LVTTL 6 mA
3-state
I/O LVTTL 3 mA
3-state
I/O LVTTL 3 mA
3-state
I/O Level Buffer type
PU/PD [kΩ]
I LVTTL –
I LVTTL –
I LVTTL –
I LVTTL –
I LVTTL –
I LVTTL –
I/O LVTTL 3 mA
3-state
PDP-5071PU
2
3
Functions
Reference clock input
Connect 24.576MHz crystal oscillator.
Reference clock output
Connect 24.576MHz crystal oscillator.
Subsequent stage line lock clock monitor input/output
It will become Hi-Z when BCK8OUT (SA1Fh, D5)=0.
Normally, set to BCK8OUT=0 and leave it open.
Functions
Front stage burst lock clock input/output
It will become Hi-Z when FCK8S[2:0] (SA21h, D6-D4)=000b.
Normally, set to FCK8S[2:0]=0 and leave it open.
Sampling clock output for µPD64031A and µPD64032
digital connection.
It will become Hi-Z when FCKQS[2:0] (SA21h, D2-D0)=000b.
Normally, set to FCKQS[2:0]=0 and leave it open.
Clamp pulse output for µPD64031A and µPD64032 digital
connection/timing output (VD) for digital RGB input.
It will become Hi-Z when FOCPS[2:0] (SA23h, D2-D0)=000b.
Normally, set to FOCPS[2:0]=0 and leave it open.
Functions
Fast Blanking signal input for analog RGB input.
YS signal input for digital RGB input.
YM signal input for digital RGB input.
Digital RGB/G signal input
Digital RGB/B signal input
Digital RGB/R signal input
Sync separation signal input/timing output (HD) for RGB input.
It will become Hi-Z when FCSIS[2:0] (SA22h, D2-D0)=000b.
Normally, set to FCSIS[2:0]=0 and leave it open.
3
4
4