HP E2444A User Manual page 48

HP E2444A
80386DX/DXL Preprocessor Interface
The preprocessor interface duplicates the internal CLK signal of the
80386DX/DXL by dividing the CLK2 signal by 2 and selecting the
correct phase of the resulting signal. This signal is called CLK and is
used to identify 80386DX/DXL activities inside the HP E2444A PAL.
The preprocessor interface detects the start of an 80386DX/DXL bus
cycle when ADS# goes true. The preprocessor interface latches
address and status on the following conditions:
•
If the 80386DX/DXL cycle is a non-pipelined cycle, address and
status are latched during the time that ADS# is low.
•
If the 80386DX/DXL cycle is a pipelined cycle, address and
status are latched during the first CLK2 cycle after READY# is
detected low.
Data is latched at the end of the 80386DX/DXL cycle. The end of the
bus cycle is defined as the rising edge of CLK2 when CLK is high and
READY# is low. The clock for the logic analyzer is generated
approximately 8 ns after the end of the cycle. The J clock for latching
information into the logic analyzer is generated by the PAL on the
HP E2444A each time the READY# signal goes low.
The K clock is for State-Per-Clock mode. It is one half the frequency
of the 80386 CLK2; however, it clocks the logic analyzer on both the
rising and the falling edges.
Figure 3-1 shows a block diagram of the HP E2444A Preprocessor
Interface. The timing diagram (figure 3-2) shows the time at which
address and data are sampled.
General Information
3-3