Additional Information On Instruction Decoding - HP E2444A User Manual

Additional
Information on
Instruction
Decoding
Note
HP E2444A
80386DX/DXL Preprocessor Interface
A 32-bit memory cycle on a 16-bit bus is sent to the logic analyzer as
two bus transactions (see figure 2-10).
The preprocessor interface stops generating logic analyzer clocks when
the 80386DX/DXL asserts HLDA. Bus cycles that assert HLDA, such
as DMA cycles, will not be captured by the logic analyzer.
The ADS and READY lines must be operating in normal
80386DX/DXL bus cycles when the HLDA line is disabled. If these
lines are not present during the HLDA (hold acknowledge) period, the
preprocessor interface will not remain in step with following bus cycles.
This will result in incorrect capturing of data.
Figure 2-10. 80386 2-Byte Mode
Analyzing the Intel 80386DX/DXL
2-17