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Instruction
Decoding (-/?)
Coprocessor
Support
Analyzing the Intel 80386DX/DXL
2-16
The HP E2444A Preprocessor Interface will send all of the bus
transactions by both the microprocessor and coprocessor to the logic
analyzer. The time count will accurately reflect when the end of the
bus cycle occurred. Prefetched instructions which are not executed by
the microprocessor are marked by a hyphen "-". Typically, several
states separate the memory (or I/O) transfer from the instruction that
caused the transfer.
The logic analyzer captures prefetches, even if they are not executed.
Care must be taken when you are specifying a trigger condition or a
storage qualification and the instruction of interest follows an
instruction that may cause branching. An unused prefetch may
generate an unwanted trigger.
Since the microprocessor only prefetches at most four words, one
technique to avoid unwanted triggering from unused prefetches is to
add "10 hex" to the trigger address. This trigger condition will only be
satisfied if the branch is not taken.
In some cases, it is impossible to determine from bus activity whether
or not a branch is taken or a prefetch is executed. In these cases, the
inverse assembler marks the disassembled line with the prefix "?".
The logic analyzer is clocked once each bus cycle. The preprocessor
interface hardware ensures that the logic analyzer will reliably capture
the address, data, and status information during both pipelined and
non-pipelined cycles by latching this information during the current bus
cycle and sending it to the logic analyzer during the succeeding bus
cycle. See the "Preprocessor Interface Description" section in Chapter
3 for complete details of this process.
The HP E2444A Preprocessor Interface and Inverse Assembler fully
supports the 80287 and 80387 math coprocessors instructions.
80386DX/DXL Preprocessor Interface
HP E2444A
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