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6-1-6. MAIN, LCD INTERFACE, VM200 (6/15)
/CS4_LCD1
[CPU_ROOT]
/CS4_LCD1
74VHCT04(5V)
/CS4_LCD2
[CPU_ROOT]
/CS4_LCD2
74VHCT04(5V)
CKIO
[CPU]
CKIO
A0
A0
RD//WR
RD//WR
5
6
U20C
9
8
U20D
4
2
D0
Q0
5
3
D1
Q0
12
7
D2
Q1
13
6
D3
Q1
10
Q2
8MHz x 4
9
11
CK
Q2
D+3.3
15
74VHCT04(5V)
Q3
1
14
RST
Q3
U19A
74VHC175(3.3V)
D+5
U20A
74VHCT04(5V)
1
2
10
C40
non
DGND
U20B
12
74VHCT04(5V)
3
4
13
C39
non
DGND
9
12
11
10
13
U23C
U23D
74VHC00(3.3V)
74VHC00(3.3V)
D[0..7]
D[0..7]
U23B
74VHC00(3.3V)
4
6
5
DGND
1
3
13
12
2
U18A
U20F
74VHC00(5V)
11
10
4
6
5
U20E
74VHCT04(5V)
U18B
74VHC00(5V)
9
8
U18C
74VHC00(5V)
11
U18D
74VHC00(5V)
D+3.3
1
VCCA
VCCB
8
2
DIR
NC
D0
3
A1
G
D1
4
A2
B1
D2
5
A3
B2
D3
6
A4
B3
D4
7
A5
B4
D5
8
A6
B5
D6
9
A7
B6
D7
10
A8
B7
11
D+3.3
GND
B8
12
GND
GND
C18
U22
0.01
TC74LVXC3245FS
DGND
DIR=L : B -> A
DIR=H : A -> B
D+5
14
VCC
C36
7
0.01
GND
C20
0.01
U18E
74VHC00(5V)
DGND
/CS_LCD1
/CS_LCD2
/CS_LCD1
/CS_LCD2
/RST
D+5
24
23
22
21
LCD_D0
LCD_D1
20
19
LCD_D2
18
LCD_D3
LCD_D4
17
16
LCD_D5
15
LCD_D6
LCD_D7
14
13
D+5
LCD_D[0..7]
C19
0.01
DGND
D+3.3
14
16
14
VCC
VCC
VCC
C37
7
8
7
0.01
GND
GND
C38
GND
0.01
U23E
U20G
U19B
74VHCT04(5V)
74VHC00(3.3V)
74VHC175(3.3V)
DGND
D+5
LCD_D0
1
TB1
LCD_D1
2
TB2
LCD_D2
3
TB3
D+5
4
LCD_D3
5
TB4
LCD_D4
6
TB5
LCD_D5
7
TB6
LCD_D6
8
TB7
LCD_D7
9
TB8
To LCD
D+5
10
D/I
11
(J1)
TB9
/LCD_WR
12
TB10
DGND
13
14
TB11
15
TB12
/RST
16
DGND
17
TB13
TB1~TB12 : 100
J15
DGND
FPC-17P
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