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6. CIRCUIT DIAGRAMS
6-1. MAIN, VM200
6-1-1. MAIN, ROOT (1/15)
MTR[0..17]
25
DGND
24
(CH1-F)
MTR0
TB20
23
(CH1-R)
MTR1
TB21
22
TB22
(CH2-F)
MTR2
21
DGND
20
MTR3
TB23
(CH2-R)
19
TB24
(CH3-F)
MTR4
18
(CH3-R)
MTR5
TB25
17
DGND
16
TB26
(CH4-F)
MTR6
15
(CH4-R)
MTR7
TB27
To FADER
14
TB28
(CH5-F)
MTR8
13
DGND
(J401)
12
(CH5-R)
MTR9
TB29
11
TB30
(CH6-F)
MTR10
10
TB31
(CH6-R)
MTR11
9
DGND
8
TB32
(CH7-F)
MTR12
7
TB33
(CH7-R)
MTR13
6
(CH8-F)
MTR14
TB34
5
DGND
4
TB35
(CH8-R)
MTR15
3
(MAS-F)
MTR16
TB36
2
TB37
(MAS-R)
MTR17
1
DGND
C25
100p
J12
12
FPC-25P
X0
DGND
13
X1
11
A
C26
AD+3.3
U11A
100p
74HC4053(3.3V)
ADGND
16
VDD
C21
0.01
8
VSS
U11D
AD+3.3
ADGND
74HC4053(3.3V)
17
VR_MAS
16
AD+3.3
15
VR_CH1
14
AD+3.3
13
VR1
12
AD+3.3
11
VR2
C27
10
AD+3.3
100p
9
VR3
To FADER
8
AD+3.3
C28
C29
(J402)
7
VR4
100p
100p
6
AD+3.3
5
VR5
4
AD+3.3
3
VR6
2
AD+3.3
1
VR7
ENC[0..23]
J13
JOG[..1]
ADGND
FPC-17P
1
(E1A)
ENC0
2
(E1B)
ENC1
3
DGND
ENCODER_IN
4
(E2A)
ENC2
5
(E2B)
ENC3
(MAIN_14/15)
6
(E3A)
ENC4
7
(E3B)
ENC5
8
(E4A)
ENC6
9
(E4B)
ENC7
10
DGND
11
(E5A)
ENC8
12
(E5B)
ENC9
13
(E6A)
ENC10
14
(E6B)
ENC11
To KEY
15
(E7A)
ENC12
(J305)
16
(E7B)
ENC13
17
DGND
18
(E8A)
ENC14
19
(E8B)
ENC15
20
(E9A)
ENC16
21
(E9B)
ENC17
22
(E10A)
ENC18
23
(E10B)
ENC19
24
DGND
25
(E11A)
ENC20
26
(E11B)
ENC21
27
(E12A)
ENC22
28
(E12B)
ENC23
29
JOG0
30
JOG1
J14
FPC-30P
DGND
/CS_DSP[0..3]
/RST_DSP
/WRQ_DSP
/WRDY_DSP
MTR[1..17]
/MUTE_ALL
/P_RST
VR_SEL_3V
W_IN_3V
14
VR0
X
/CS_DIF
7
VEE
6
INH
CPU_ROOT
ADGND
(MAIN_2/15)
VR[0..7]
VR[0..7]
C33
100p
LRCK
C30
C31
C32
100p
100p
100p
A[0..19]
ADGND
D[0..31]
/RD
/WR
/RST_3V
ENC[0..23]
/RST
SCKDSP_3V
JOG[..1]
TXDDSP_3V
/ENC[0..23]
/ENC[0..23]
/ENC[0..23]
TXDDISP_3V
/ATN1_DISP
/JOG0
/JOG0
/JOG0
SCK_DISP
/JOG1
/JOG1
/JOG1
/CS5
/CS6
POWER
RXD2_3V
/ATN2_DISP3V
(MAIN_15/15)
/CS_DSP[0..3]
/RST_DSP
/WRQ_DSP
/WRDY_DSP
/MUTE_ALL
/P_RST
AD_D[0..3]
PRE_EQ_D[0..7]
VR_SEL_3V
VR_SEL_3V
SPDIF_D
ST_D
W_IN_3V
W_IN_3V
/RST_EQ
/CS_DIF
GA(DIF)
/CS_DIF
(MAIN_11/15)
ADAT_D[0..3]
A[0..19]
ADAT_D[0..3]
SYS_LRCK
D[0..31]
SYS_LRCK
WORD_INT
WORD_INT
/RD
MSCK
/WR
MSCK
BCK
BCK
LRCK
/RST_3V
LRCK
LRCK
A[0..19]
D[0..31]
/RD
/WR
/RST_3V
/RST
SCKDSP_3V
TXDDSP_3V
TXDDISP_3V
1
TB14
/RST
2
TXD_DISP
TB15
3
TB16
RXD_DISP
4
TB17
SCK_DISP
To KEY
5
/ATN1_DISP
TB18
(J301)
6
TB19
/ATN2_DISP
7
DGND
8
DGND
TB15, TB16 : 100
J11
DGND
FPC-8P
/CS5
/CS6
RXD2_3V
/ATN2_DISP_3V
/PD_DSP
AD_D[0..3]
PRE_EQ_D[0..7]
SPDIF_D
ST_D
/RST_EQ
/PD_DSP
POST_EQ_[0..7]
ADAT_D[0..3]
POST_EQ_[0..7]
AUX12_D
SYS_LRCK
AUX12_D
AUX34_D
WORD_INT
AUX34_D
MON_D
MON_D
ST_D
MSCK
ST_D
BCK
FXS_D
LRCK
FXS_D
LRCK
FXR_D0
FXR_D0
FXR_D1
FXR_D1
SPPS
LRCK2
LRCK2
BCK2
(MAIN_13/15)
BCK2
/FULL_EQ
/FULL_EQ
/+48X_ON
A[0..19]
/+48X_ON
D[0..31]
/RD
/WR
/RST_3V
/RST
SCKDSP_3V
TXD_DSP
TXDDSP_3V
TXD_DSP
SCK_DSP
SCK_DSP
TXDDISP_3V
TXD_DISP
RXD_DISP
/ATN2_DISP
/CS5
/CS6
RXD2_3V
/ATN2_DISP_3V
/CS_DSP[0..3]
/PD_DSP
/RST_DSP
/WRQ_DSP
/WRDY_DSP
TXD_DSP
SCK_DSP
/MUTE_ALL
/P_RST
AD_D[0..3]
PRE_EQ_D[0..7]
SPDIF_D
ST_D
/RST_EQ
DSP_ROOT
(MAIN_7/15)
POST_EQ_[0..7]
AUX12_D
AUX34_D
MON_D
ST_D
FXS_D
FXR_D0
FXR_D1
LRCK2
BCK2
/FULL_EQ
/+48X_ON
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